CMSC 2100 Logic and Switching Theory
Welcome
Catalog Description
Course Outcomes
Instructor
Text
Grades
Homework
Tests
Cheating
Using AI
Attendance
Disabilties
Title IX
PennWest Policies
Course Outline
Notes
Course Outline
Numbers
Introduction and Representation of Information
Representation based on distinguish ability
Representation based on application
Representation based on arithmetic
Representation based on error control
Integer Base Conversion
Binary to decimal
Base x to decimal
Decimal to binary
Decimal to base x
Fraction Base Conversion
Binary to decimal
Base x to decimal
Decimal to binary
Decimal to base x
Notations and Conversions
Hexadecimal and binary
Octal and binary
Base y and base x
Codes and Conversions
Non-weighted codes
ASCII
EBCDIC
Gray
Parity
Weighted codes
BCD
2421
642-3
2-out-of-5
Binary Arithmetic operations
Addition
Subtraction
Sign magnitude
1's complement notation
2's complement notation
Binary Functions
Functional components
Combinational
Storage
Switching functions
AND
OR
INVERTER
NAND
NOR
XOR
XNOR
Combinational networks and expressions
Network diagrams
Expressions
Switching Algebra
Boolean connectives
DeMorgan
Normal form
Standard form
Combinational Networks
Analysis
Synthesis
Translate Networks to all NANDs or all NORs
Minimization Techniques
Karnaugh maps
Karnaugh maps and don't cares
Quine-McCluskey
Quine-McCluskey and don't cares
Combinational Modules
Encoders
Decoders
Transcoders
Multiplexers
Demultiplexers
ROMs
PLAs
Synchronous Sequential Networks
Timing diagrams
Latch (Flip Flops)
RS
Master Slave
D
JK
T
Registers
Analysis of sequential networks
State transition tables
State transition diagrams
Synthesis of sequential networks
Stuck states
Two level (AND OR) design
Design using combinational modules
Asynchronous Sequential Networks
Analysis
Synthesis
Revised Spring 2006