Computer Architecture

Course Outline

Hypothetical Computer
1. Introduction to a computer with the IPO cycle
2. Assembly language instruction set and machine language representation
  1. Data transfer group
  2. Arithmetic and logic group
  3. Control group
3. Instruction formats
4. Programming with a minimal instruction set
5. Fetch execute cycle
Binary Arithmetic
1. Addition, subtraction and 2's complement
2. Full adder combinational network
3. Carry look ahead addition
  1. Carry look ahead adder
  2. Carry look ahead generator
4. Arithmetic logic unit
5. Logic unit
6. Shifter unit
7. Multiplication
  1. Hardware
  2. Software
CPU and Memory
1. Register transfer language
2. Microsequence signals
3. Memory organization
4. CPU structure
5. Index registers and related instructions
6. Subroutine implementation
7. Addressing mode
Control Unit
1. Microsequence implementation and control signals
2. Translation of machine instructions to microsequences
3. Control unit
  1. Discrete sequential machine
  2. One-hot assignment sequencer
  3. ROM based sequential machine
4. Microprogramming of the control unit
Extending Generic CPU Concepts to Specialty Structures
Date Transfer Rates
1. Input/output control
2. Data transfer rate calculations

Revised 2012