Overview of a CPU

• Central Processing Unit.
• We discussed direction in class briefly.
  • We have learned how to design and minimize our own circuits.
  • But there a number of basic circuits that we can use.
  • We are to study these circuits next.
  • I would like to provide an example where we will use many of these circuits.
• A simple CPU
  • For reference, we will be playing with my virtual implementation of Ben Eater's 8 bit computer..
  • I have a version of this, but I have not yet assembled it.
  • I have a javascript implementation here that we will use.
  • This is a work in progress, and I would appreciate any feedback you wish to provide.
• An abstract simple cpu.
  • This consists of eight components.
    • A program counter (pc), or instruction pointer (ip), which points to the address of the next instruction in memory.
      • This is a special purpose register.
      • We will discuss registers at the end of the semester.
    • An instruction register (ir), this is a special purpose register that holds the current instruction we are executing.
    • At least one general purpose register (acc, or Rn (where n is a register number)
    • An arithmetic logic unit (alu) that can perform mathematical operations.
    • A memory management unit (mmu) that interacts with memory
      • The memory address register (mar) contains the address in memory this unit interacts with.
      • The memory data register (mdr) contains the data to send to / receive from memory.
    • Memory is outside of the CPU but is
    • The control unit (cu) controls the entire operation.
    • The bus connects all of these.
• The Fetch-decode-execute cycle
  • The cpu runs the following program

    while not halt
      get the instruction from memory pointed to by the PC
      PC++
      decode the instruction
      execute the instruction.
            

• RTN (register transfer notation)
  • The above algorithm is somewhat abstract so we use a semi-formal notation to show what is happening.
  • In the form dest ← source
  • For example: bus ← pc indicates that the cpu should move the value of the pc to the bus.
• Fetch:

  • bus ← pc
    mar ← bus
    pc ← pc + 1
    memory fetch
    bus ← mdr
    ir ← bus
            

  • pc ← pc+1 is hardware dependent.
    • It depends on how memory is addressed and instruction size.
    • For now we will assume a 1.
• We can write all instructions in rtn, which gives us the execute part of the fetch decode execute cycle.
• The instruction set, along with rtn for the 8-bit computer is here
• Trace the program
  • cout << 3 + 2

  • 0: Load 5 
    1: Add  4
    2: Output
    3: Halt
    4: 2
    5: 3 

  • For the simulator this would be

    0x15 0x24 0xe0 0xf0 0x02 0x03