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SAP-db ISA

Note: this specification has been created from Ben Eaters 8-bit Computer videos. I have attempted to recreate this computer here.

Functional Units

The 8-bit computer has the following functional units:

• A single 8 bit register called the Accumulator. This is sometimes refered to as the A register.
• The ALU
  • The ALU supports
    • Addition/Subtraction
    • Zero detection
    • Overflow detection.
  • The second input to the ALU is a register called the B register.
• An 8 bit program counter register
  • This includes an adder to increment by 1
• An 8 bit instruction register
• A 2⁴ = 16 words of RAM.

Instructions

Each instruction is a single 8 bit word. The top for bits (instruction<7..4>) are the op code. The bottom four bits (instruction<3..0>) are the operand.

All values are padded with zero. So the address would be 00000000+instruction<3..0>

Opcode	Ben Nmeonic	Dan Nmeonic	Operand	Description
0000	NOP	NOP		Do Nothing
0001	LDA	Load	Source Memory Address	Load the data from memory into the A register
0010	ADD	Add	Memory Address	Add the contents of memory to the contents of the A register and store it into the A register.
0011	SUB	Subtract	Memory Address	Subtract the contents of membory from the contents of the A register and store it into the A register.
0100	STA	Store	Destination Memory Address	Store the contents of the A register at the destination address in memory
0101	LDI	LoadI	a 4 bit number	Load the A reister with the 4 bit immediate. The top bits are 0
0110	JMP	Jump	Instruction Addres	Jump to the specified address.
0111	JC	JumpC	Instruction Address	Jump if the carry bit is set
1000	JZ	JumpZ	Instruction Address	Jump if the value of the A register is zero.
1001	NOP	NOP
1010	NOP	NOP
1011	NOP	NOP
1100	NOP	NOP
1101	NOP	NOP
1110	OUT	Output		Display the value (as an integer) stored in the A register
1111	HLT	Halt		Stop Operation

RTN

• Fetch

  IR ← MPC]
  
   BUS ← PC
   MAR ← BUS 
   enable memory load
   BUS ← MDR
   IR ← BUS
  
  PC ← PC + 1
  
   Enable PC increment
  
     

• ADD

  Acc ← Acc + M[IR<3..0>]
  
   fetch
   BUS ← IR<3..0>
   MAR ← BUS
   enable memory load
   BUS ← MDR
   B ← BUS
   ALU OP ADD
   BUS ← ALU
   Acc ← BUS
  

• SUBTRACT

  Acc ← Acc - M[IR<3..0>]
  
   fetch
   BUS ← IR<3..0>
   MAR ← BUS
   enable memory load
   BUS ← MDR
   B ← BUS
   ALU OP SUBTRACT 
   BUS ← ALU
   Acc ← BUS
  

• Load

  Acc ← M[IR<3..0>]
  
   BUS ← IR<3...0>
   MAR ← BUS
   enable memory load
   BUS ← MDR
   Acc ← BUS
  
  

• Store

  M[IR<3..0>] ← Acc
  
   BUS ← IR<3..0>
   MAR ← BUS
   BUS ← Acc
   MDR ← BUS
   enable memory store
  
  

• LoadI

  Acc ← IR<3..0>
  
   BUS ← IR<3..0>
   Acc ← bus
  
  

• Jump

  PC ← IR<3..0>
  
   BUS ← IR<3..0>
   PC ← BUS
  
  

• JumpC

  if overflow
     PC ← IR<3..0>
  
  overflow : BUS ← IR<3..0>
  overflow : PC ← BUS 
  
  

• JumpZ

  if Acc == 0
     PC ← IR<3..0>
  
  ACC=0: BUS ← IR<3..0>
  ACC=0: PC ← BUS
  
  

• Output

   BUS ← Acc
   IOReg ← BUS
   Raise output signal