//: version "1.8.2"

module main;    //: root_module
wire w6;    //: /sn:0 {0}(80,99)(85,99)(85,86)(90,86){1}
wire Q0;    //: /sn:0 /dp:2 {0}(192,80)(209,80)(209,73){1}
//: {2}(211,71)(233,71)(233,64){3}
//: {4}(207,71)(166,71)(166,55)(171,55){5}
wire Clock;    //: /sn:0 /dp:2 {0}(-3,96)(19,96){1}
//: {2}(23,96)(59,96){3}
//: {4}(21,94)(21,81)(90,81){5}
//: {6}(21,98)(21,110)(27,110){7}
wire w4;    //: /sn:0 /dp:1 {0}(171,82)(154,82){1}
wire Q;    //: /sn:0 /dp:3 {0}(171,77)(161,77)(161,68)(210,68)(210,55){1}
//: {2}(212,53)(220,53)(220,46){3}
//: {4}(208,53)(192,53){5}
wire w3;    //: /sn:0 /dp:1 {0}(59,101)(56,101)(56,110)(48,110){1}
wire w0;    //: /sn:0 /dp:1 {0}(171,50)(153,50){1}
wire D;    //: /sn:0 /dp:2 {0}(133,79)(127,79)(127,54){1}
//: {2}(129,52)(132,52){3}
//: {4}(125,52)(45,52){5}
wire w5;    //: /sn:0 {0}(111,84)(118,84){1}
//: {2}(120,82)(120,47)(132,47){3}
//: {4}(120,86)(120,84)(133,84){5}
//: enddecls

  and g4 (.I0(Clock), .Z(w3));   //: @(38,110) /sn:0 /delay:" 20" /w:[ 7 1 ]
  //: joint g8 (Q) @(210, 53) /w:[ 2 -1 4 1 ]
  and g13 (.I0(Clock), .I1(w6), .Z(w5));   //: @(101,84) /sn:0 /w:[ 5 1 0 ]
  led g3 (.I(Q0));   //: @(233,57) /sn:0 /w:[ 3 ] /type:0
  led g2 (.I(Q));   //: @(220,39) /sn:0 /w:[ 3 ] /type:0
  or g1 (.I0(!Q), .I1(!w4), .Z(Q0));   //: @(182,80) /sn:0 /w:[ 0 0 0 ]
  //: joint g11 (w5) @(120, 84) /w:[ -1 2 1 4 ]
  //: joint g10 (Clock) @(21, 96) /w:[ 2 4 1 6 ]
  nand g6 (.I0(w5), .I1(D), .Z(w0));   //: @(143,50) /sn:0 /w:[ 3 3 1 ]
  //: joint g9 (Q0) @(209, 71) /w:[ 2 -1 4 1 ]
  nand g7 (.I0(!D), .I1(w5), .Z(w4));   //: @(144,82) /sn:0 /w:[ 0 5 1 ]
  //: joint g5 (D) @(127, 52) /w:[ 2 -1 4 1 ]
  //: switch D (D) @(28,52) /w:[ 5 ] /st:1
  or g0 (.I0(!w0), .I1(!Q0), .Z(Q));   //: @(182,53) /sn:0 /w:[ 0 5 5 ]
  //: switch CLOCK (Clock) @(-20,96) /w:[ 0 ] /st:1
  xor g12 (.I0(Clock), .I1(w3), .Z(w6));   //: @(70,99) /sn:0 /w:[ 3 0 0 ]

endmodule