Modeling Performance

• Convert Clock speed (MHz) to cycle length
• Convert Memory speed (MHz) to cycle length
• Computer memory delay cycles.
• For each class
  • Cycles per step
  • Memory Cycles
  • Non Memory Time
  • Memory Time
  • Total Time
  • Time With Fetch
  • Instruction Count
  • Instruction Probability
• Average Cycle Time
• Mips
  • With instruction count
  • With Instruction Probability
  • With/Without memory
• Ratio with mem to without mem
• Instruction Mix
  • This is monstly a guess, we would have to study the usage pattern of the machine for this to be completely correct
  • This is taken (modified) from Hennesy and Patterson

  • Instruction	Frequency
    Load	26%
    Store	9%
    Math	27%
    Compare	24%
    Jump	1%
    Indirect Add	10%

  • Note, for the tables in H and P, there is no indirect instruction, so I am really guessing here.
• 
• My computation in excel

Microcode

• Note, our control unit could really be a program
• In each state
  • Execute a set number of commands (light control lines)
  • Examine the op code and possibly control lines to determine the next state
• Essentially, our control unit has a Program Counter (or state register)
• We need an instruction that performs the two actions above
• This instruction needs to
  • Light the proper control lines
  • Move to the next state.
• This is actually not that difficult
• It allows us to "reprogram" the computer,
  • Fix bugs in the design
  • add instructions
• It makes the machine slower
• It is not used in pipelining

Interrupts

• Also called Exceptions and Traps
• Interrupts occur when something out of order happens within the cpu
  • An I/O device needs service
  • Overflow, division by 0
  • Other hardware errors, (memory fails a parity check)
  • Invalid Instructions
  • Page Faults
• The machine must handle these problems or perform a hardware interrupt
• Some of them are maskable - or can be ignored
• Others are unmaskable - or can not be ignored
• With MARIE, interrupts are handled at the top of the F-E cycle
  • Check for an interrupt, if found handle it
  • Otherwise continue with next Fetch
• Most often, signals are indicated by a flag set in a status register
• Interrupts are handled by interrupt routines
  • The current PC, and registers are saved
  • The address of the interrupt routine is located
  • The interrupt routine is executed
  • The PC and registers are restored
• Interrupt addresses are often stored in an array or trap vector

Assemblers

• Why assemblers?
  • Forget their arguments about how you can do better then the compiler
  • This takes really specialized training
  • Plus, machines will ignore you anyway
  • But that is for another architecture class
• What nice things do we want an assembler to do?
  • Make it so we don't have to memorize machine code
  • Make it so we don't have to work out the math for
    • Variable addresses
    • Jump destinations
• Changing Mnemonics to opcodes is an easy table lookup
• Changing symbolic addresses to actual addresses is more tricky
  • On pass 1, build a symbol table
  • For each name you encounter
    • If it is not in the table add it
    • If it is defined, add the address
  • On pass 2, output opcodes and operands by consulting the symbol table
• We might also do something about providing more instructions
  • For example, we might have a branch on zero (BOZ) which becomes the proper skipcond
  • We might have a comment instruction, which we just strip off as we assemble