Pipelining

• Does instruction fetch depend on the other parts of execution?
• The machine is broken into stages, or pipeline stages
• We will consider
  • Instruction Fetch
  • Instruction Decode
  • ALU - all math operations, includes address calculaton
  • Result Save - includes data memory access.
• Notice that each piece is independant.
• 
• The boxes on the stage line are called latches.
• Data path, instruction path.

• Instruction	Stage 1	Stage 2	Stage 3	Stage 4
  op R4,R3,R2	Fetch	R2, R3 to latch	op	Result stored in R4
  ldw R6,R1,R5	Fetch	R1 R5 to latch	ADD	Fetch data at computed address, store in R6
  bne offset	Fetch	pc, const to latch	ADD	sum to pc

• An example execution
  • Consider the following code:

          set R1, 100
          set R2, 20
          set R3, -2
          set R4, 0
    top:  sub R0, R2, R0
          beq out
          ldw R5, R1,R2
          add R4,R4,R5
          add R2,R2,R3
          bra top
    out:
         

  • So the execution will be:

    Time	Fetch	Decode	ALU	Save
    t0	set R1, 100
    t1	set R2, 20	set R1, 100
    t2	set R3, -2	set R2, 20	set R1, 100
    t3	set R4, 0	set R3, -2	set R2, 20	set R1, 100
    t4	sub R0, R2, R0	set R4, 0	set R3, -2	set R2, 20

  • We could change this table:  

    Stage	t0	t1	t2	t3
    Fetch	set R1, 100	set R2,20	set R3,-2	set R4,0
    Decode		set R1, 100	set R2,20	set R3,-2
    ALU			set R1, 100	Set R2,20
    Save				set R1, 100

• So what does this save us?
  • Can we perform any single instruction faster?
  • After 4 cycles we have completed 1 instruction
  • After 5 cycles we have completed 2 instructions
  • After 6 cycles we have completed 3 instructions
  • After n cycles we have completed n-3 instructions.
  • As n becomes large, we come close to an instruction per cycle.
  • Except...