//: version "1.6i" module delay(); //: interface /sz:(40, 40) /bd:[ ] //: enddecls endmodule module ctrl(ck, s, c, r, w); //: interface /sz:(40, 40) /bd:[ ] input w; //: /sn:0 {0}(36,125)(53,125)(53,133)(86,133){1} //: {2}(90,133)(117,133)(117,116)(136,116){3} //: {4}(88,135)(88,153)(127,153){5} input r; //: /sn:0 /dp:1 {0}(127,163)(58,163){1} //: {2}(56,161)(56,126)(136,126){3} //: {4}(54,163)(39,163){5} input ck; //: /sn:0 {0}(61,45)(52,45)(52,48){1} //: {2}(54,50)(61,50){3} //: {4}(50,50)(36,50){5} //: {6}(52,52)(52,111)(136,111){7} output s; //: /sn:0 {0}(199,147)(219,147){1} input c; //: /sn:0 {0}(39,138)(80,138){1} //: {2}(84,138)(114,138)(114,121)(136,121){3} //: {4}(82,140)(82,158)(127,158){5} wire w7; //: /sn:0 {0}(148,158)(168,158)(168,149)(178,149){1} wire w4; //: /sn:0 /dp:1 {0}(134,56)(125,56)(125,53){1} //: {2}(127,51)(134,51){3} //: {4}(123,51)(118,51){5} wire w3; //: /sn:0 {0}(157,121)(176,121)(176,144)(178,144){1} wire w2; //: /sn:0 {0}(155,54)(165,54)(165,69)(126,69)(126,131)(136,131){1} wire w5; //: /sn:0 {0}(82,48)(89,48){1} //: {2}(93,48)(97,48){3} //: {4}(91,50)(91,53)(97,53){5} //: enddecls //: joint g8 (w) @(88, 133) /w:[ 2 -1 1 4 ] and g4 (.I0(ck), .I1(!w), .I2(c), .I3(r), .I4(w2), .Z(w3)); //: @(147,121) /sn:0 /w:[ 7 3 3 3 1 0 ] //: input g13 (ck) @(34,50) /sn:0 /w:[ 5 ] //: output g3 (s) @(216,147) /sn:0 /w:[ 1 ] //: input g2 (c) @(37,138) /sn:0 /w:[ 0 ] //: input g1 (r) @(37,163) /sn:0 /w:[ 5 ] //: joint g11 (ck) @(52, 50) /w:[ 2 1 4 6 ] //: joint g10 (w4) @(125, 51) /w:[ 2 -1 4 1 ] nor g19 (.I0(w3), .I1(w7), .Z(s)); //: @(189,147) /sn:0 /w:[ 1 1 0 ] //: joint g6 (r) @(56, 163) /w:[ 1 2 4 -1 ] //: joint g7 (c) @(82, 138) /w:[ 2 -1 1 4 ] and g9 (.I0(ck), .I1(ck), .Z(w5)); //: @(72,48) /sn:0 /w:[ 0 3 0 ] and g15 (.I0(w4), .I1(w4), .Z(w2)); //: @(145,54) /sn:0 /w:[ 3 0 0 ] //: joint g14 (w5) @(91, 48) /w:[ 2 -1 1 4 ] and g5 (.I0(w), .I1(c), .I2(!r), .Z(w7)); //: @(138,158) /sn:0 /w:[ 5 5 0 0 ] //: input g0 (w) @(34,125) /sn:0 /w:[ 0 ] and g12 (.I0(w5), .I1(w5), .Z(w4)); //: @(108,51) /sn:0 /w:[ 3 5 5 ] endmodule module main; //: root_module supply0 w2; //: /sn:0 {0}(143,76)(143,66)(135,66){1} supply0 w11; //: /sn:0 {0}(156,136)(156,125)(150,125){1} supply0 w13; //: /sn:0 {0}(298,68)(298,65)(287,65){1} wire w6; //: /sn:0 {0}(308,125)(308,161){1} //: {2}(306,163)(299,163){3} //: {4}(308,165)(308,194)(216,194){5} //: {6}(212,194)(144,194)(144,209)(134,209){7} //: {8}(214,196)(214,205){9} wire [7:0] w7; //: /sn:0 {0}(111,81)(111,110){1} wire [7:0] w14; //: /sn:0 {0}(263,80)(263,155){1} wire w16; //: /sn:0 {0}(239,65)(229,65){1} wire cs; //: /sn:0 {0}(207,255)(207,261)(116,261)(116,238){1} wire w3; //: /sn:0 {0}(169,115)(166,115){1} //: {2}(162,115)(150,115){3} //: {4}(164,117)(164,178)(113,178)(113,196){5} wire w20; //: /sn:0 {0}(283,163)(268,163){1} wire [7:0] w1; //: /sn:0 {0}(95,32)(95,52){1} wire [7:0] w8; //: /sn:0 {0}(279,28)(279,51){1} wire [7:0] w12; //: /sn:0 /dp:1 {0}(231,228)(312,228){1} //: {2}(316,228)(347,228)(347,29){3} //: {4}(314,226)(314,187)(263,187)(263,171){5} wire clk; //: /sn:0 /dp:5 {0}(42,120)(57,120){1} //: {2}(61,120)(74,120){3} //: {4}(59,122)(59,214)(92,214){5} wire w10; //: /sn:0 /dp:1 {0}(221,255)(221,260)(240,260){1} //: {2}(244,260)(253,260){3} //: {4}(242,262)(242,283)(153,283)(153,225)(134,225){5} wire [7:0] w5; //: /sn:0 /dp:1 {0}(127,52)(127,43)(159,43){1} //: {2}(163,43)(224,43){3} //: {4}(228,43)(247,43)(247,51){5} //: {6}(226,45)(226,166)(181,166){7} //: {8}(177,166)(111,166)(111,131){9} //: {10}(179,168)(179,228)(196,228){11} //: {12}(161,41)(161,28){13} wire w9; //: /sn:0 {0}(87,66)(77,66){1} //: enddecls add g4 (.A(w1), .B(w5), .S(w7), .CI(w2), .CO(w9)); //: @(111,68) /sn:0 /w:[ 1 0 0 1 0 ] //: joint g8 (w5) @(161, 43) /w:[ 2 12 1 -1 ] //: supply0 g3 (w11) @(156,142) /sn:0 /w:[ 0 ] //: joint g13 (clk) @(59, 120) /w:[ 2 -1 1 4 ] not g2 (.I(w6), .Z(w20)); //: @(293,163) /sn:0 /R:2 /w:[ 3 0 ] register g1 (.Q(w5), .D(w7), .EN(w11), .CLR(w3), .CK(clk)); //: @(111,120) /sn:0 /w:[ 9 1 1 3 3 ] led PC (.I(w5)); //: @(161,21) /w:[ 13 ] /type:1 //: switch Clear (w3) @(187,115) /R:2 /w:[ 0 ] /st:1 bufif1 g16 (.Z(w12), .I(w14), .E(w20)); //: @(263,161) /sn:0 /R:3 /w:[ 5 1 1 ] //: joint g11 (w10) @(242, 260) /w:[ 2 -1 1 4 ] //: joint g10 (w5) @(179, 166) /w:[ 7 -1 8 10 ] //: joint g19 (w3) @(164, 115) /w:[ 1 -1 2 4 ] //: dip g6 (w1) @(95,22) /sn:0 /w:[ 0 ] /st:1 ram g9 (.A(w5), .D(w12), .WE(w6), .OE(w10), .CS(cs)); //: @(214,229) /sn:0 /w:[ 11 0 9 0 0 ] ctrl g7 (.c(w3), .ck(clk), .r(w10), .w(w6), .s(cs)); //: @(93, 197) /sz:(40, 40) /sn:0 /p:[ Ti0>5 Li0>5 Ri0>5 Ri1>7 Bo0<1 ] //: joint g15 (w5) @(226, 43) /w:[ 4 -1 3 6 ] //: switch Read (w10) @(271,260) /R:2 /w:[ 3 ] /st:1 //: dip g17 (w8) @(279,18) /sn:0 /w:[ 0 ] /st:3 //: supply0 g5 (w2) @(143,82) /sn:0 /w:[ 0 ] add g14 (.A(w5), .B(w8), .S(w14), .CI(w13), .CO(w16)); //: @(263,67) /sn:0 /w:[ 5 1 0 1 0 ] //: joint g21 (w12) @(314, 228) /w:[ 2 4 1 -1 ] led MEM (.I(w12)); //: @(347,22) /w:[ 3 ] /type:1 //: switch Write (w6) @(308,112) /R:3 /w:[ 0 ] /st:1 clock g0 (.Z(clk)); //: @(29,120) /sn:0 /w:[ 0 ] /omega:400 /phi:0 /duty:50 //: supply0 g22 (w13) @(298,74) /sn:0 /w:[ 0 ] //: joint g12 (w6) @(308, 163) /w:[ -1 1 2 4 ] //: joint g18 (w6) @(214, 194) /w:[ 5 -1 6 8 ] endmodule module Delay(del, Signal); //: interface /sz:(40, 40) /bd:[ Ti0>Signal(17/40) Bo0