//: version "1.6i"

module PC(dl6, dl5, cl9, cl3, cl2, ol2);
//: interface  /sz:(40, 40) /bd:[ ]
supply0 w3;    //: /sn:0 {0}(425,435)(425,420)(412,420){1}
input [7:0] dl6;    //: /sn:0 {0}(307,270)(363,270)(363,298){1}
input ol2;    //: /sn:0 {0}(430,348)(436,348)(436,410)(412,410){1}
supply0 w1;    //: /sn:0 {0}(419,286)(419,255)(407,255){1}
input cl3;    //: /sn:0 {0}(311,415)(336,415){1}
input cl9;    //: /sn:0 {0}(308,314)(350,314){1}
output [7:0] dl5;    //: /sn:0 {0}(542,457)(522,457){1}
input cl2;    //: /sn:0 {0}(497,409)(514,409)(514,452){1}
wire [7:0] w6;    //: /sn:0 {0}(367,216)(367,241){1}
wire [7:0] w0;    //: /sn:0 {0}(383,270)(383,298){1}
wire [7:0] w12;    //: /sn:0 /dp:1 {0}(373,405)(373,327){1}
wire w2;    //: /sn:0 {0}(340,255)(359,255){1}
wire [7:0] w5;    //: /sn:0 /dp:5 {0}(373,426)(373,457)(456,457){1}
//: {2}(460,457)(506,457){3}
//: {4}(458,455)(458,223)(399,223)(399,241){5}
//: enddecls

  //: input g4 (dl6) @(305,270) /sn:0 /w:[ 0 ]
  //: joint g8 (w5) @(458, 457) /w:[ 2 4 1 -1 ]
  //: supply0 g13 (w3) @(425,441) /sn:0 /w:[ 0 ]
  //: output g3 (dl5) @(539,457) /sn:0 /w:[ 0 ]
  //: input g2 (cl9) @(306,314) /sn:0 /w:[ 0 ]
  //: input g1 (cl3) @(309,415) /sn:0 /w:[ 0 ]
  bufif1 g11 (.Z(dl5), .I(w5), .E(cl2));   //: @(512,457) /sn:0 /w:[ 1 3 1 ]
  //: dip g10 (w6) @(367,206) /w:[ 0 ] /st:1
  add g6 (.A(w6), .B(w5), .S(w0), .CI(w1), .CO(w2));   //: @(383,257) /sn:0 /w:[ 1 5 0 1 1 ]
  mux g7 (.I0(dl6), .I1(w0), .S(cl9), .Z(w12));   //: @(373,314) /sn:0 /w:[ 1 1 1 1 ]
  //: supply0 g9 (w1) @(419,292) /sn:0 /w:[ 0 ]
  //: comment g14 /dolink:0 /link:"" @(497,256) /sn:0 /R:3
  //: /line:"dl5  PC to bus"
  //: /line:"dl6  bus to PC"
  //: /line:""
  //: /line:"cl2  PC to bus"
  //: /line:"cl3  load pc"
  //: /line:"cl9  INC to PC  (not BUS to PC)"
  //: /end
  register g5 (.Q(w5), .D(w12), .EN(w3), .CLR(ol2), .CK(cl3));   //: @(373,415) /sn:0 /w:[ 0 0 1 1 1 ]
  //: input g0 (cl2) @(495,409) /sn:0 /w:[ 0 ]
  //: input g12 (ol2) @(428,348) /sn:0 /w:[ 0 ]

endmodule

module ALU(cl10, dl13, dl12, dl14);
//: interface  /sz:(94, 75) /bd:[ Ti0>dl12[7:0](76/94) Bi0>cl10[1:0](71/94) Bi1>dl13[7:0](20/94) Lo0<dl14[7:0](27/75) ]
supply1 w3;    //: /sn:0 {0}(297,212)(297,232)(281,232){1}
input [1:0] cl10;    //: /sn:0 {0}(244,340)(295,340){1}
input [7:0] dl13;    //: /sn:0 {0}(127,180)(154,180){1}
//: {2}(158,180)(239,180){3}
//: {4}(243,180)(350,180){5}
//: {6}(354,180)(415,180)(415,214){7}
//: {8}(352,182)(352,214){9}
//: {10}(241,182)(241,218){11}
//: {12}(156,182)(156,218){13}
supply0 w17;    //: /sn:0 {0}(214,254)(214,232)(196,232){1}
output [7:0] dl14;    //: /sn:0 {0}(363,383)(318,383)(318,353){1}
input [7:0] dl12;    //: /sn:0 /dp:12 {0}(127,142)(186,142){1}
//: {2}(190,142)(271,142){3}
//: {4}(275,142)(382,142){5}
//: {6}(386,142)(447,142)(447,214){7}
//: {8}(384,144)(384,214){9}
//: {10}(273,144)(273,218){11}
//: {12}(188,144)(188,218){13}
wire [7:0] w14;    //: /sn:0 {0}(257,247)(257,285)(312,285)(312,324){1}
wire w16;    //: /sn:0 {0}(233,232)(223,232){1}
wire w4;    //: /sn:0 {0}(148,232)(138,232){1}
wire [7:0] w15;    //: /sn:0 /dp:1 {0}(300,324)(300,300)(172,300)(172,247){1}
wire [7:0] w19;    //: /sn:0 {0}(324,324)(324,283)(368,283)(368,243){1}
wire [7:0] w11;    //: /sn:0 {0}(421,243)(421,253){1}
wire [7:0] w10;    //: /sn:0 {0}(441,243)(441,302)(336,302)(336,324){1}
//: enddecls

  //: supply0 g4 (w17) @(214,260) /sn:0 /w:[ 0 ]
  //: input g8 (cl10) @(242,340) /sn:0 /w:[ 0 ]
  add g3 (.A(dl13), .B(!dl12), .S(w14), .CI(w3), .CO(w16));   //: @(257,234) /sn:0 /w:[ 11 11 0 1 0 ]
  //: joint g13 (dl13) @(352, 180) /w:[ 6 -1 5 8 ]
  div g2 (.A(dl13), .B(dl12), .Q(w10), .R(w11));   //: @(431,230) /sn:0 /w:[ 7 7 0 0 ]
  mult g1 (.A(dl13), .B(dl12), .P(w19));   //: @(368,230) /sn:0 /w:[ 9 9 1 ]
  //: joint g16 (dl12) @(273, 142) /w:[ 4 -1 3 10 ]
  //: input g11 (dl13) @(125,180) /sn:0 /w:[ 0 ]
  //: input g10 (dl12) @(125,142) /sn:0 /w:[ 0 ]
  mux g6 (.I0(w15), .I1(w14), .I2(w19), .I3(w10), .S(cl10), .Z(dl14));   //: @(318,340) /sn:0 /w:[ 0 1 0 1 1 1 ]
  //: comment g7 /dolink:0 /link:"" @(238,351) /sn:0
  //: /line:"ADD 00"
  //: /line:"SUB 01"
  //: /line:"MPY 10"
  //: /line:"DIV 11"
  //: /line:""
  //: /end
  //: output g9 (dl14) @(360,383) /sn:0 /w:[ 0 ]
  //: joint g15 (dl12) @(188, 142) /w:[ 2 -1 1 12 ]
  //: joint g17 (dl12) @(384, 142) /w:[ 6 -1 5 8 ]
  //: supply1 g5 (w3) @(308,212) /sn:0 /w:[ 0 ]
  //: joint g14 (dl13) @(156, 180) /w:[ 2 -1 1 12 ]
  add g0 (.A(dl13), .B(dl12), .S(w15), .CI(w17), .CO(w4));   //: @(172,234) /sn:0 /w:[ 13 13 1 1 0 ]
  //: comment g18 /dolink:0 /link:"" @(66,312) /sn:0 /R:3
  //: /line:"CL10  ALUOP (10 and 11)"
  //: /line:""
  //: /line:"dl12 BUSTOALU"
  //: /line:"dl13 ACCTOALU"
  //: /line:"dl14 ALUTOACC"
  //: /line:""
  //: /end
  //: joint g12 (dl13) @(241, 180) /w:[ 4 -1 3 10 ]

endmodule

module ACC(dl1, cl8, cl1, cl0, dl4, dl3, ol2, dl2);
//: interface  /sz:(84, 95) /bd:[ Ti0>dl1[7:0](58/84) Li0>cl8(69/95) Li1>cl1(51/95) Li2>cl0(33/95) Bi0>ol2(32/84) Ri0>dl2[7:0](42/95) To0<dl4[7:0](19/84) Bo0<dl3[7:0](62/84) ]
input cl8;    //: /sn:0 {0}(147,216)(184,216){1}
input cl1;    //: /sn:0 {0}(136,269)(170,269){1}
output [7:0] dl4;    //: /sn:0 {0}(311,341)(285,341){1}
supply0 w3;    //: /sn:0 {0}(269,275)(269,274)(246,274){1}
input [7:0] dl2;    //: /sn:0 {0}(161,156)(217,156)(217,200){1}
input [7:0] dl1;    //: /sn:0 {0}(159,179)(197,179)(197,200){1}
input cl0;    //: /sn:0 {0}(251,319)(277,319)(277,336){1}
input ol2;    //: /sn:0 {0}(258,243)(268,243)(268,264)(246,264){1}
output [7:0] dl3;    //: /sn:0 /dp:1 {0}(269,341)(207,341)(207,304){1}
//: {2}(209,302)(254,302){3}
//: {4}(207,300)(207,280){5}
wire [7:0] w8;    //: /sn:0 {0}(207,229)(207,259){1}
//: enddecls

  //: comment g4 /dolink:0 /link:"" @(285,147) /sn:0 /R:3
  //: /line:"cl0 ACC-> BUS"
  //: /line:"cl1 LOAD ACC"
  //: /line:"cl8 ALU-> ACC"
  //: /line:""
  //: /line:"dl1 BUSTOACC"
  //: /line:"dl2 ALUTOACC"
  //: /line:"dl3 ACCTOALU"
  //: /line:"dl4 ACCTOBUS"
  //: /line:""
  //: /end
  //: joint g8 (dl3) @(207, 302) /w:[ 2 4 -1 1 ]
  bufif1 g3 (.Z(dl4), .I(dl3), .E(cl0));   //: @(275,341) /sn:0 /w:[ 1 0 1 ]
  //: input g13 (dl1) @(157,179) /sn:0 /w:[ 0 ]
  //: supply0 g2 (w3) @(269,281) /sn:0 /w:[ 0 ]
  register g1 (.Q(dl3), .D(w8), .EN(w3), .CLR(ol2), .CK(cl1));   //: @(207,269) /sn:0 /w:[ 5 1 1 1 1 ]
  //: input g11 (cl8) @(145,216) /sn:0 /w:[ 0 ]
  //: input g10 (cl1) @(134,269) /sn:0 /w:[ 0 ]
  //: input g6 (cl0) @(249,319) /sn:0 /w:[ 0 ]
  //: output g7 (dl4) @(308,341) /sn:0 /w:[ 0 ]
  mux g9 (.I0(dl1), .I1(dl2), .S(cl8), .Z(w8));   //: @(207,216) /sn:0 /w:[ 1 1 1 0 ]
  //: output g5 (dl3) @(251,302) /sn:0 /w:[ 3 ]
  //: input g0 (ol2) @(256,243) /sn:0 /w:[ 0 ]
  //: input g12 (dl2) @(159,156) /sn:0 /w:[ 0 ]

endmodule

module MMU(cl13, ol2, cl5, cl14, cl7, cl6, dl9, ol1, dl11);
//: interface  /sz:(100, 100) /bd:[ Ti0>dl9[7:0](18/100) Bi0>ol2(24/100) Ri0>cl5(17/100) Ri1>cl6(37/100) Ri2>cl13(57/100) Ri3>cl14(77/100) Ri4>cl7(48/100) Bo0<ol1(70/100) Tt0=dl11[7:0](52/100) ]
inout [7:0] dl11;    //: /sn:0 {0}(500,25)(510,25)(510,94){1}
//: {2}(508,96)(301,96)(301,105){3}
//: {4}(510,98)(510,132){5}
supply0 w4;    //: /sn:0 {0}(356,193)(356,188)(340,188){1}
input ol2;    //: /sn:0 {0}(166,152)(182,152){1}
//: {2}(186,152)(356,152)(356,178)(340,178){3}
//: {4}(184,154)(184,175)(182,175){5}
supply0 w1;    //: /sn:0 {0}(193,192)(193,185)(182,185){1}
input cl7;    //: /sn:0 /dp:1 {0}(346,267)(364,267){1}
//: {2}(368,267)(372,267){3}
//: {4}(366,265)(366,113)(306,113){5}
input cl6;    //: /sn:0 /dp:1 {0}(505,140)(475,140)(475,120){1}
output ol1;    //: /sn:0 {0}(249,374)(215,374){1}
input cl14;    //: /sn:0 {0}(225,217)(225,211)(294,211){1}
//: {2}(298,211)(443,211)(443,85)(273,85)(273,90){3}
//: {4}(296,213)(296,286){5}
//: {6}(294,288)(271,288){7}
//: {8}(296,290)(296,309){9}
//: {10}(294,311)(235,311){11}
//: {12}(296,313)(296,339)(319,339){13}
input [7:0] dl9;    //: /sn:0 {0}(96,162)(143,162)(143,170){1}
input cl13;    //: /sn:0 {0}(319,344)(129,344){1}
//: {2}(127,342)(127,282){3}
//: {4}(129,280)(178,280){5}
//: {6}(127,278)(127,268)(53,268)(53,80)(268,80)(268,90){7}
//: {8}(125,280)(107,280){9}
//: {10}(127,346)(127,371)(167,371){11}
//: {12}(171,371)(194,371){13}
//: {14}(169,373)(169,376)(194,376){15}
input cl5;    //: /sn:0 {0}(95,180)(106,180){1}
wire w7;    //: /sn:0 {0}(271,111)(271,138){1}
wire w3;    //: /sn:0 {0}(255,288)(232,288)(232,278){1}
//: {2}(234,276)(276,276)(276,245){3}
//: {4}(232,274)(232,267){5}
wire MDR_CLOCK;    //: /sn:0 {0}(393,270)(412,270)(412,57)(215,57)(215,183)(264,183){1}
wire [7:0] intoreg;    //: /sn:0 /dp:5 {0}(301,121)(301,141){1}
//: {2}(299,143)(279,143){3}
//: {4}(301,145)(301,173){5}
wire [7:0] outofreg;    //: /sn:0 {0}(301,194)(301,238){1}
//: {2}(303,240)(510,240)(510,148){3}
//: {4}(299,240)(284,240){5}
wire [7:0] w2;    //: /sn:0 /dp:1 {0}(268,240)(251,240){1}
//: {2}(249,238)(249,143)(263,143){3}
//: {4}(247,240)(242,240){5}
wire w12;    //: /sn:0 {0}(340,342)(350,342)(350,272)(372,272){1}
wire [7:0] address;    //: /sn:0 /dp:1 {0}(143,191)(143,240)(207,240){1}
wire w9;    //: /sn:0 {0}(194,280)(218,280)(218,267){1}
//: enddecls

  //: input g4 (cl13) @(105,280) /sn:0 /w:[ 9 ]
  //: input g8 (ol2) @(164,152) /sn:0 /w:[ 0 ]
  //: joint g37 (cl14) @(296, 211) /w:[ 2 -1 1 4 ]
  bufif1 g34 (.Z(w2), .I(outofreg), .E(w3));   //: @(278,240) /sn:0 /R:2 /w:[ 0 5 3 ]
  bufif1 g13 (.Z(dl11), .I(outofreg), .E(cl6));   //: @(510,142) /sn:0 /R:1 /w:[ 5 3 0 ]
  //: input g3 (cl5) @(93,180) /sn:0 /w:[ 0 ]
  register g2 (.Q(outofreg), .D(intoreg), .EN(w4), .CLR(ol2), .CK(MDR_CLOCK));   //: @(301,183) /sn:0 /w:[ 0 5 1 3 1 ]
  register g1 (.Q(address), .D(dl9), .EN(w1), .CLR(ol2), .CK(cl5));   //: @(143,180) /sn:0 /w:[ 0 1 1 5 1 ]
  bufif1 g16 (.Z(intoreg), .I(dl11), .E(cl7));   //: @(301,111) /sn:0 /R:3 /w:[ 0 3 5 ]
  not g11 (.I(cl14), .Z(w3));   //: @(265,288) /sn:0 /R:2 /w:[ 7 0 ]
  and g28 (.I0(cl14), .I1(cl13), .Z(w12));   //: @(330,342) /sn:0 /delay:" 90" /w:[ 13 0 0 ]
  //: input g10 (cl14) @(233,311) /sn:0 /w:[ 11 ]
  and g19 (.I0(cl13), .I1(!cl14), .Z(w7));   //: @(271,101) /sn:0 /R:3 /w:[ 7 3 0 ]
  bufif1 g32 (.Z(intoreg), .I(w2), .E(w7));   //: @(269,143) /sn:0 /w:[ 3 3 1 ]
  or g27 (.I0(cl7), .I1(w12), .Z(MDR_CLOCK));   //: @(383,270) /sn:0 /delay:" 20" /w:[ 3 1 0 ]
  //: supply0 g6 (w1) @(193,198) /sn:0 /w:[ 0 ]
  //: joint g9 (ol2) @(184, 152) /w:[ 2 -1 1 4 ]
  //: supply0 g7 (w4) @(356,199) /sn:0 /w:[ 0 ]
  //: joint g31 (outofreg) @(301, 240) /w:[ 2 1 4 -1 ]
  //: input g20 (cl7) @(344,267) /sn:0 /w:[ 0 ]
  //: joint g15 (dl11) @(510, 96) /w:[ -1 1 2 4 ]
  //: joint g25 (cl13) @(127, 344) /w:[ 1 2 -1 10 ]
  //: joint g29 (cl14) @(296, 311) /w:[ -1 9 10 12 ]
  //: input g17 (cl6) @(475,118) /sn:0 /R:3 /w:[ 1 ]
  //: joint g14 (intoreg) @(301, 143) /w:[ -1 1 2 4 ]
  not g5 (.I(cl13), .Z(w9));   //: @(184,280) /sn:0 /w:[ 5 0 ]
  //: joint g36 (cl13) @(169, 371) /w:[ 12 -1 11 14 ]
  //: joint g24 (cl13) @(127, 280) /w:[ 4 6 8 3 ]
  //: input g21 (dl9) @(94,162) /sn:0 /w:[ 0 ]
  and g23 (.I0(cl13), .I1(cl13), .Z(ol1));   //: @(205,374) /sn:0 /delay:" 110" /w:[ 13 15 1 ]
  //: joint g35 (w3) @(232, 276) /w:[ 2 4 -1 1 ]
  //: output g26 (ol1) @(246,374) /sn:0 /w:[ 0 ]
  //: inout g22 (dl11) @(494,25) /sn:0 /w:[ 0 ]
  ram g0 (.A(address), .D(w2), .WE(cl14), .OE(w3), .CS(w9));   //: @(225,241) /sn:0 /w:[ 1 5 0 5 1 ]
  //: joint g18 (cl7) @(366, 267) /w:[ 2 4 1 -1 ]
  //: joint g12 (cl14) @(296, 288) /w:[ -1 5 6 8 ]
  //: joint g30 (w2) @(249, 240) /w:[ 1 2 4 -1 ]

endmodule

module main;    //: root_module
wire [1:0] w6;    //: /sn:0 {0}(177,282)(177,294)(132,294)(132,249){1}
wire w7;    //: /sn:0 {0}(-135,-76)(-123,-76)(-123,-63)(-116,-63){1}
wire w14;    //: /sn:0 {0}(-124,211)(-111,211){1}
wire [7:0] w16;    //: /sn:0 {0}(-91,122)(-91,159){1}
wire w15;    //: /sn:0 {0}(-124,244)(-119,244)(-119,229)(-111,229){1}
wire [7:0] w19;    //: /sn:0 {0}(-31,132)(-31,150)(-52,150)(-52,159){1}
wire [7:0] w4;    //: /sn:0 {0}(60,200)(47,200)(47,155){1}
wire w0;    //: /sn:0 {0}(-135,-44)(-116,-44){1}
wire w3;    //: /sn:0 {0}(-78,256)(-78,324)(454,324)(454,-121)(-78,-121){1}
//: {2}(-82,-121)(-136,-121){3}
//: {4}(-80,-119)(-80,-75){5}
wire [7:0] w1;    //: /sn:0 /dp:1 {0}(137,172)(137,141){1}
wire w8;    //: /sn:0 {0}(-135,-12)(-126,-12)(-126,-16)(-116,-16){1}
wire [7:0] w18;    //: /sn:0 {0}(15,103)(15,202)(-25,202){1}
wire [7:0] w17;    //: /sn:0 {0}(15,238)(15,267)(-48,267)(-48,256){1}
wire [7:0] w2;    //: /sn:0 {0}(-32,19)(-32,31)(-80,31)(-80,19){1}
wire [7:0] w11;    //: /sn:0 {0}(36,299)(36,316)(81,316)(81,249){1}
wire w13;    //: /sn:0 {0}(-125,145)(-115,145)(-115,193)(-111,193){1}
wire [7:0] w5;    //: /sn:0 {0}(-129,59)(-129,63)(-75,63)(-75,36)(-102,36)(-102,19){1}
//: enddecls

  led g4 (.I(w2));   //: @(-32,12) /sn:0 /w:[ 0 ] /type:1
  //: switch g8 (w8) @(-152,-12) /sn:0 /w:[ 0 ] /st:1
  PC g3 (.ol2(w3), .cl9(w8), .cl3(w0), .cl2(w7), .dl6(w5), .dl5(w2));   //: @(-115, -74) /sz:(51, 92) /sn:0 /p:[ Ti0>5 Li0>1 Li1>1 Li2>1 Bi0>1 Bo0<1 ]
  //: switch g13 (w14) @(-141,211) /sn:0 /w:[ 0 ] /st:1
  //: comment g2 /dolink:0 /link:"" @(-49,-107) /sn:0
  //: /line:"Other Lines"
  //: /line:"  MMU: "
  //: /line:"     ol1  memory done"
  //: /line:"     ol2  clear all registers"
  //: /line:""
  //: /end
  //: comment g1 /dolink:0 /link:"" @(296,-88) /sn:0
  //: /line:"Data Lines"
  //: /line:"ACC:"
  //: /line:"  dl1  BUSTOACC"
  //: /line:"  dl2  ALUTOACC"
  //: /line:"  dl3  ACCTOALU"
  //: /line:"  dl4  ACCTOBUS"
  //: /line:""
  //: /line:"PC:"
  //: /line:"  dl5  PCTOBUS"
  //: /line:"  dl6  BUSTOPC"
  //: /line:""
  //: /line:"CU:"
  //: /line:"  dl7  BUSTOIR"
  //: /line:"  dl8  ADDRTOBUS"
  //: /line:""
  //: /line:"MMU:"
  //: /line:"  dl9  BUSTOMAR"
  //: /line:"  dl11 MDRTOBUS"
  //: /line:""
  //: /line:"   "
  //: /line:"ALU:"
  //: /line:"  dl12 BUSTOALU"
  //: /line:"  dl13 ACCTOALU"
  //: /line:"  dl14 ALUTOACC"
  //: /end
  //: joint g11 (w3) @(-80, -121) /w:[ 1 -1 2 4 ]
  led g16 (.I(w17));   //: @(15,231) /sn:0 /w:[ 0 ] /type:1
  ACC g10 (.dl1(w19), .cl8(w15), .cl1(w14), .cl0(w13), .ol2(w3), .dl2(w18), .dl4(w16), .dl3(w17));   //: @(-110, 160) /sz:(84, 95) /sn:0 /p:[ Ti0>1 Li0>1 Li1>1 Li2>1 Bi0>0 Ri0>1 To0<1 Bo0<1 ]
  ALU g19 (.dl12(w1), .cl10(w6), .dl13(w11), .dl14(w4));   //: @(61, 173) /sz:(94, 75) /sn:0 /p:[ Ti0>0 Bi0>1 Bi1>1 Lo0<0 ]
  //: switch g6 (w0) @(-152,-44) /sn:0 /w:[ 0 ] /st:1
  //: switch g7 (w7) @(-152,-76) /sn:0 /w:[ 0 ] /st:1
  //: switch g9 (w3) @(-153,-121) /sn:0 /w:[ 3 ] /st:1
  led g15 (.I(w16));   //: @(-91,115) /sn:0 /w:[ 0 ] /type:1
  //: dip g20 (w1) @(137,131) /sn:0 /w:[ 1 ] /st:2
  //: dip g17 (w18) @(15,93) /sn:0 /w:[ 0 ] /st:16
  //: dip g5 (w5) @(-129,49) /sn:0 /w:[ 0 ] /st:0
  //: switch g14 (w15) @(-141,244) /sn:0 /w:[ 0 ] /st:1
  //: dip g21 (w11) @(36,289) /sn:0 /w:[ 0 ] /st:6
  //: dip g23 (w6) @(177,272) /sn:0 /w:[ 0 ] /st:0
  //: comment g0 /dolink:0 /link:"" @(175,-111) /sn:0
  //: /line:"Control Lines (From BOOK)"
  //: /line:""
  //: /line:"ACC:"
  //: /line:"  cl0   ACC->BUS "
  //: /line:"  cl1   load ACC"
  //: /line:"  cl8   ALU->ACC"
  //: /line:""
  //: /line:"PC:"
  //: /line:"  cl2   PC->BUS"
  //: /line:"  cl3   load PC"
  //: /line:"  cl9   inc PC"
  //: /line:""
  //: /line:"CU:"
  //: /line:"  cl4   LOAD IR"
  //: /line:"  cl12  Addr->BUS"
  //: /line:""
  //: /line:"MMU:"
  //: /line:"  cl5   LOAD MAR"
  //: /line:"  cl6   MDR->BUS"
  //: /line:"  cl7   LOAD MDR"
  //: /line:"  cl13  CS"
  //: /line:"  cl14  R/notW"
  //: /line:""
  //: /line:"ALU:"
  //: /line:"  cl10  ALUOP"
  //: /line:"  cl11  ALUOP"
  //: /end
  led g22 (.I(w4));   //: @(47,148) /sn:0 /w:[ 1 ] /type:1
  //: switch g12 (w13) @(-142,145) /sn:0 /w:[ 0 ] /st:1
  //: dip g18 (w19) @(-31,122) /sn:0 /w:[ 0 ] /st:255

endmodule