Chapter 3, Basic Components

Goals
- Describe how to each of the following could be constructed
  - Memory Subsystem
  - CPU
  - Basic I/O Device interface.
  - I/O Bus
- Describe the parts of a simple CPU.
- Describe the operation of a simple computer.
- Describe the ISA for our simple machine.
- Describe the Fetch/Execute Cycle
Intro
- In chapter 2, we discovered how we can build simple circuits.
- In this chapter will will use these simple circuits to construct a very simple computer.
- This machine consists of a memory system, and a cpu
- We will also take a very quick look at I/O devices and an I/O bus.
- This is only an intro to the CPU, we will continue to build on this for the rest of the class.
- There are a number of issues we will not address here, including secondary storage, cache, networking.
Memory
- Getting Started
  - Remember Flip Flops?
  - Registers?
  - These are memory units in the CPU
  - They are expensive, and fast.
  - In this section, we will consider main memory
  - Much larger (sparc 32x64 bits in registers vs 4GB possible main memory)
  - Much Slower (clock speed vs 20-200ns)
  - Much less expensive
    - This is somewhat complex, and beyond the scope of this class.
    - In general, the number of registers in a CPU is tied to to the complexity of both the instruction set and the CPU design.
  - We will not consider cache here.
    - Memory between registers and main memory
    - Still located on the chip, but not part of the cpu.
    - celeron, pentium, xeon.
    - This issue is fairly complex and does not need to be discussed for basic understanding.
  - Take Arch II for both of these (and many other fascinating issues)
- Terms
  - Memory is a collection of bits.
  - Generaly, we don't address memory on the bit level.
  - We usually access memory in a small collection of bits
  - The number of bits in this uint is the memory width
  - Typicaly this is 8 bits, (size of a character drives this)
  - This type of memory is byte addressable, and indicates a memory width of 8
  - Memory can be considered an array of bytes, starting at 0 and going through n-1, where n is the number of bytes in memory.
  - This is called an n x w memory.
  - For example, 1024 bits (2¹⁰) of memory can be configured as
    - 1 x 1024
    - 2 x 512
    - 4 x 256
    - 8 x 128
  - Memory supports two operations
    - Read the value stored at an address.
    - Write a value to an address in memory.
    - Read is also called fetch, or load.
    - Write is also called store, or save.
    - ```
    void write(mem_value_t val, mem_address_t addr);
    mem_value_t read(mem_address_t addr);
    	    
```
- There are a number of types of memory:
  - Random Access Memory (RAM)
    - Access to any address requires equivelent time
    - Not like a tape.
    - Sometimes called direct access memoary.
    - Generaly we can read/write to this memory
    - This is general purpose memory, and what we will mostly be concerned with.
  - Read Only Memory (ROM)
    - Origanaly - values are permenantly stored in this memory.
    - Random access in nature, but you can't write to it.
    - Used to perminantly store a program
      
      Atari 6400 games (and all other non-cd rom based games)
      Boot instructions for a intell box (and other machines)
      POST
      Boot instructions for perpherial devices (Plug and Play)
      BIOS
    - PROM - Programmable Read Only Memory
      
      Like first family of writeable cd's
      WORM - write once read many
    - EPROM - Erasable PROM
      
      Remove the WORM, but requires special device to erase
    - EEPROM - Electronicaly EPROM
    - Flash Memory
    - Flash your BIOS.
  - Volatile - nonvolatile
    - nonvolatile - the vale persists over a loss of power
    - volatile - it does not.
- Operaton
  - For our purposes memory has four interfaces:
    - An address port
      - If we have n bits in the address, there are n input lines on this port.
      - For every operation, the cpu places the address of the memory it wishes to access on these lines.
      - These lines are labeled A₀ ... A_n-1
    - A data port
      - For a w bit wide memory, there are w data lines.
      - Labeled D₀ through D_w-1
      - The CPU reads data from/ writes data to these lines
    - A chip select line
      - The cpu uses this line to signal to the memory that it is set to perform a task.
      - 0 - not ready, 1 - ready
    - A read/ not write line
      - CPU uses this line to signal operation
      - 1 = read
      - 0 = write
      - Why is it called read /not write
    - To read a w-bit unit from memory
```
Put the address on A₀ through A_n-1
Raise the R/ not W line
Raise CS
Wait
Read the value on D₀ through D_w-1
Lower CS and R/not W
	    
```
    - To write to memory
```
Put the address on A₀ through A_n-1
Put the data on D₀ through D_w-1
Raise CS
Wait
Lower CS

	    
```
  - Access Time is the time from the start of a read operation until the data is available.
  - Cycle time is the time from the start of an operation until the operation is complete
  - Cycle time may be larger than access time, as some types of memory require extra time for housekeeping.
    - Read may be destructive
    - Memory may need to be refreshed to keep the values consistant
  - Our author discusses DRAM vs SRAM. This is discussion is dated.
  - One of the dangers of reading about architecture is Moore's Law, which applies to memory as well as the CPU.
  - Memory sizes, speeds, and prices are outdated as soon as they are published.
  - For our discussion, we will look at DRAM
    - This memory had a destructive read.
    - It needs to be reloaded after we read.
    - The added complexity is not too much, and is interesting to look at.
- Organization
  - Basic DRAM cell
    - Each cell contains a single bit.
    - Each cell has
      - A Data line D
      - A Control line S
    - When S is raised to 1
      - The cell writes its value to the D line.
      - The cell reads a value from the D line.
    - To read:
```
raise S
Read the value on D
Put the value back on D
Lower S
	      
```
    - To Write:
```
Raise S
Wait
Put the new value on D
Lower S
	      
```
    - To accomplish this, we will assume circuitry exists to perform the sense/write operation.
      - Inputs:
        
        Data from a memory cell
        CS
        Read/Not Write
        Data to store to the cell.
      - Output:
        
        Data to return to the cell.
        Data to send to the data lines.
      - This is a possible implementation of the Sense/write logci.
  - We can now build a simple memory circuit.
  - This is called a 2D orgnization since the memory is arranged in rows and columns
  - The lines out of the decoder are called word select lines
  - The lines to/from the sense/write logic are called bit lines
  - The size of this memory is restricted due to complexity of
    - The number of lines into/out of the chip
    - n+w+4 lines are needed. (RS, R/W, ground power)
    - The complexity of the decoder
    - A n bit decoder requires 2ⁿ and gates.
  - The more square memory is the fewer gates in the decoder
  - The more liner memory is the fewer pins needed.
  - A different arrangement allows to minimize both the size of the decoder and the number of pins used.
    - Use a mux for datain and data out
      - Data is sent in/out over a single pin
      - This solves the pin count problem
      - This slows memory down.
      - This is called 2 1/2 D memory.
    - For this to work, we think of the memory as 1x4096
    - But the actual chip is 64x64
    - We send a series of w bits and addresses to store/retreive a word.
    - Physical word size = 64
    - Logical word size = 1