Midterm Exam, CSCI 312, Fall 2016

• Make sure you answer each question completely and thoughtfully.
• Please make sure your answers are clearly labeled with the question number.
• Please write neatly and make any diagrams as neat as you can. If I can't read it, it is wrong.
• Point values are listed by each question.

1. WOMBAT architecture (a WOMBAT instruction set reference is attached)
   1. [5 points] Describe, in low level WOMBAT RTN, what must occur in the fetch phase of the fetch-decode-execute cycle for WOMBAT.
   2. The current WOMBAT instruction set consists of 15 instructions. You have decided to add two more instructions to this set. Assume that the instruction size must remain 16 bits.
      1. [3 points] Give a new instruction format to accommodate this change.
      2. [4 points] What impact will this have on the operation of the machine?
   3. [3 points] One of the Eight Great Ideas in Computer Architecture is to achieve Performance via Parallelism. Where is this idea employed in the WOMBAT architecture.

2. [4 points] Draw a diagram representing the current Memory Hierarchy.
   1. Describe elements at each level.
   2. Describe what happens in terms of cost, speed and size at the different levels of this hierarchy.
3. [8 points] Name the four hardware/software components our authors describe as having an effect on the CPI. Describe the impact of each component.
4. Two implementations of the same program have the following characteristics:

   Implementation	CPI	Instruction Count
   A	3.2	3.0 x 10 6
   B	2.1	2.6 x 10 6

   These two implementation are running on a processor with a 3GHz clock.
   1. [3 points] Compute the length of a single cycle of the clock in appropriate units. Show your work.
   2. [4 points] Compute the time required for each implementation to execute the program. Show your work.
   3. [3 points] Which implementation has the better performance? Explain why.
5. [5 points] Explain why clock speed is an insufficient measurement of CPU performance.
6. [8 points] MUX
   1. Describe the operation of a 2 input MUX.
   2. Describe the input and output lines used in a 2 input MUX.
   3. Using and, or and not gates, draw a circuit for a 2 input MUX.
   4. What purpose does a MUX serve in a CPU implementation?