Final Exam, CSCI 312, Fall 2016

• Make sure you answer each question completely and thoughtfully.
• Please make sure your answers are clearly labeled with the question number.
• Please write neatly and make any diagrams as neat as you can. If I can't read it, it is wrong.
• Point values are listed by each question.
• Please answer the question asked. A shotgun approach, or simply writing everything you know about a topic is not acceptable.
• Show all work, answers without supporting computations are worth 0 credit.

1. [6 points] On the attached worksheet trace the execution of lw $t4, 10($t3).
   • Show the value for all data and control lines except ALUOp and the output of ALU control.
   • Assume each register holds 100 * the register address, so $v0 holds 200.
   • Assume that each memory location holds 1000 plus the address. So memory location 5 holds 1005.
   • Write data values on the boxes provided.

2. [10 points] Name and describe elements of the MIPS ISA which are present to support function calls. Describe why each is required.

3. [3 points] Name and describe three types of hazards introduced by pipelining a processor.

4. Select one type of hazard from above.
   1. State the type of hazard you have selected.

   2. [4 points] Give an example of MIPS assembly language code which causes this type of hazard. Clearly describe ALL occurrences of this hazard in your code.

   3. [4 points] Draw a timing diagram for your code. The columns should be labeled with the stage of the processor and the rows should be labeled with time. Instructions should be either I_n for instruction n, or a circle for a bubble. Assume no hazard mitigation occurs.

   4. [3 points] Describe how your selected hazard can be mitigated.

   5. [3 points] Describe any circumstances where your selected hazard can not be mitigated.

5. [8 points] Assume a single cycle non-pipelined processor has a clock speed of 1.2 ns. Assuming that this processor can be converted into a six stage pipeline, where each stage requires 1/6 of the clock cycle of the single cycle cpu. Additionally assume no additional time is required to implement the pipeline. Finally assume a CPI of 1 for the non-pipelined processor and a CPI of 1.2 for the pipelined processor. If a program ran in 60ms on the non-pipelined processor, compute the time and speedup for this program on the pipelined processor.

6. [3 points] An item may not be present in cache for three reasons. Name and describe each.

7. Assume a memory latency of 15ns and a clock cycle of 250ps in a piplined architecture. Further assume one pipeline stage is dedicated to memory access.
   1. [3 points] Compute the cache miss penalty in terms of clock cycles.

   2. [3 points] Assuming the cache hit rate is 85% and that all memory access instructions suffer cache misses equally, what is the CPI for memory access instructions?