Pipelines

• Five arbitrary instructions through the single machine
  • Assume each takes 200 ps except for ID/WB
  • IF, ID, EX, MEM, WB
• Repeat for pipeline
• Show three ways to represent this process.
• Trace the following code

• lw    $t1, 100($t5)
  add   $t2, $t1, $t2
  sw    $t2, 100($t5)
      

• This is a Data Hazard or an instruction in the pipeline must wait for second instruction to complete to produce the data needed by the first instruction.
• What if we used the ALU to increment the PC
• This is a Structural Hazard or two instructions need the same hardware to execute
  • We have a single structural hazard, the register file
  • We declare that instructions in WB save the data during the first half of the instruction cycle
  • Then instructions in ID can access the data in the second half of the instruction cycle.
• Trace the following

• beq	$t1, $t2, done
  lw	$t2, 100($t2)
      

• This is a Control Hazard which occurs when it is not known if the instruction(s) following a conditional branch should be executed or not.
• In addition, unless we are careful, we can have control hazards following unconditional jumps as well
  • But you know about that (sort of)
  • What strange thing occurs with jal? Why?