The Pipeline Datapath and Control

• From last time
  • If a program takes 3x10⁹ instructions and has an effective CPI of 1. What is the time required if the program
    1. Runs on a non-pipelined processor with a clock speed of 800ps.

                     
         	                   1 cycle       800 ps
          3x109 instructions x ------------- x ------ =  800x 3x109ps
                               1 instruction   1 cycle
       
       		= 2.4 x 1012 ps x 1 second / 1x1012ps
       		= 2.4 sec 
       

    2. Runs on a pipelined processor with a clock speed of 200ps.

          One instruction will require 1000ps or 800 extra ps
          One instruction will require  800ps or 600 extra ps
          One instruction will require  600ps or 400 extra ps
          One instruction will require  400ps or 200 extra ps
                                               ------
       					 2000 extra ps
       
          3x109-4 instructions will require 200ps.  SO
                                  1 cycle      200ps
          3x109 instructions x ------------- x ------- = 3 x 200 x 109ps
                               1 instruction  1 cycle 
       		= 6 x 1011 ps x 1 second /1x1012ps
       		= .6 second - 2000 ps
       		= .6 seconds
       	
       

• In section 4.6 they note
  • All data and control flows from left to right
    • Except the pc which is possibly computed in the ex stage
    • And the data for the register file in writeback
  • Pipeline registers are placed in-between each stage of the pipeline
    • These reigsters hold both data and control information from the previous stage.
    • These registers are labled by the stages they are between
    • See the picture on page 304.
    • Trace add $t3, $t2, $s1 through this.
    • Trace anything else needed through this.
• How could we insert a buble into this pipeline?
  • Not allow any changes to the "state" of the computation by the bubble
    • Don't allow any memory writes so set MEMWrite to be 0
    • Don't allow any changes to a regiseter so set RegWrite to be 0
    • Don't allow the PC to increment
    • Don't allow any other changes (IE Jumps and such)
  • Don't save any stalled instructions to the next stage pipeline registers.
• Data hazards
  • This is section 4.7
  • Data hazards occur because data that is needed is not in the register file.
  • What produces data for the register file?
  • Can you think of a set of instructions which cause a data hazard for each data source?
  • How big is the delay for each data source?
  • Can we do a quick computation of the impact.
  • Data forwarding can handle most most data hazards by detecting data dependancies.
    • They introduce a notation to represent registers in the pipeline
      • PIPELINE_REGISTER_NAME.REGISTER_NUMBER
      • If lw $t2,3($t5) is in the ID/EX stage
        • ID/EX.RegisterRS = $t5
        • ID/EX.RegisterRD = $t2
  • What are the data dependancies?

    lw   $t1, 4($t3)
    addi $t1, $t3,  23
    sw   $t1, 4($t3)
    add  $t1, $t2, $t3
    add  $t3, $t1, $t1
    add  $t5, $t1, $t1
    lw   $t2, 7($t5)