//: version "2.0-b10" //: property encoding = "iso8859-1" //: property locale = "en" //: property prefix = "_GG" //: property title = "MIPS_ALUC.v" //: property timingViolationMode = 2 //: property initTime = "0 ns" `timescale 1ns/1ns //: /netlistBegin main module main; //: root_module reg w14; //: /sn:0 {0}(338,791)(338,776)(249,776)(249,676){1} //: {2}(251,674)(341,674)(341,689){3} //: {4}(249,672)(249,581){5} //: {6}(251,579)(341,579)(341,595){7} //: {8}(249,577)(249,475){9} //: {10}(251,473)(341,473)(341,499){11} //: {12}(249,471)(249,450)(209,450){13} reg w3; //: /sn:0 {0}(157,137)(157,103)(140,103)(140,63)(114,63){1} reg [3:0] w0; //: /sn:0 {0}(#:127,657)(127,619)(#:144,619){1} reg w24; //: /sn:0 {0}(292,595)(292,592)(232,592){1} //: {2}(230,590)(230,485){3} //: {4}(232,483)(295,483)(295,499){5} //: {6}(228,483)(218,483)(218,496)(211,496){7} //: {8}(230,594)(230,679){9} //: {10}(232,681)(292,681)(292,689){11} //: {12}(230,683)(230,784)(289,784)(289,791){13} reg w1; //: /sn:0 {0}(130,186)(73,186)(73,203)(63,203){1} reg [3:0] w18; //: /sn:0 {0}(#:138,807)(132,807)(#:132,754){1} reg [1:0] w30; //: /sn:0 {0}(#:317,42)(317,122)(297,122)(#:297,137){1} reg [1:0] w17; //: /sn:0 {0}(#:426,791)(426,775)(499,775)(499,677){1} //: {2}(499,673)(499,587){3} //: {4}(499,583)(499,484){5} //: {6}(499,480)(#:499,463){7} //: {8}(497,482)(428,482)(#:428,499){9} //: {10}(497,585)(432,585)(#:432,595){11} //: {12}(497,675)(432,675)(#:432,689){13} reg w11; //: /sn:0 {0}(130,156)(78,156)(78,142)(68,142){1} reg w12; //: /sn:0 {0}(233,47)(243,47)(243,137){1} reg w5; //: /sn:0 {0}(382,499)(382,450)(357,450){1} reg w9; //: /sn:0 {0}(186,76)(206,76)(206,137){1} wire w6; //: /sn:0 {0}(150,604)(165,604)(165,517)(269,517){1} wire w32; //: /sn:0 {0}(144,822)(192,822)(192,847)(255,847){1} wire w7; //: /sn:0 {0}(358,210)(358,228)(243,228)(243,213){1} wire w19; //: /sn:0 {0}(265,614)(150,614){1} wire w37; //: /sn:0 {0}(461,856)(536,856)(536,913)(74,913)(74,560)(269,560){1} wire w21; //: /sn:0 {0}(378,671)(378,689){1} wire w31; //: /sn:0 {0}(255,811)(199,811)(199,634)(150,634){1} wire w28; //: /sn:0 {0}(523,695)(523,728)(465,728){1} wire w23; //: /sn:0 {0}(518,879)(518,892)(372,892)(372,877){1} wire w36; //: /sn:0 {0}(527,535)(527,538)(473,538){1} wire w20; //: /sn:0 {0}(265,644)(188,644)(188,802)(144,802){1} wire w25; //: /sn:0 {0}(265,708)(213,708)(213,624)(150,624){1} wire w35; //: /sn:0 {0}(385,575)(385,584)(377,584)(377,595){1} wire w8; //: /sn:0 {0}(379,148)(379,176)(330,176){1} wire w22; //: /sn:0 {0}(523,619)(523,634)(465,634){1} wire w10; //: /sn:0 {0}(269,538)(182,538)(182,792)(144,792){1} wire w13; //: /sn:0 {0}(378,791)(378,765){1} wire w29; //: /sn:0 {0}(523,769)(523,835)(461,835){1} wire w26; //: /sn:0 {0}(265,738)(195,738)(195,812)(144,812){1} //: enddecls //: SWITCH g4 (w11) @(51,142) /sn:0 /w:[ 1 ] /st:0 /dn:1 //: LED g8 (w7) @(358,203) /sn:0 /w:[ 0 ] /type:0 //: joint g3 (w24) @(230, 681) /w:[ 10 9 -1 12 ] //: joint g13 (w14) @(249, 473) /w:[ 10 12 -1 9 ] //: DIP B (w18) @(132,744) /w:[ 1 ] /st:0 /dn:0 //: SWITCH g2 (w9) @(169,76) /sn:0 /w:[ 0 ] /st:0 /dn:1 //: SWITCH g1 (w3) @(97,63) /sn:0 /w:[ 1 ] /st:0 /dn:1 //: joint g16 (w17) @(499, 675) /w:[ -1 2 12 1 ] //: joint g11 (w14) @(249, 579) /w:[ 6 8 -1 5 ] //: DIP A (w0) @(127,668) /R:2 /w:[ 0 ] /st:11 /dn:0 //: SWITCH g10 (w1) @(46,203) /sn:0 /w:[ 1 ] /st:0 /dn:1 ALU0 g27 (.ainvert(w24), .Cin(w5), .Operation(w17), .binvert(w14), .less(w37), .a(w6), .b(w10), .Cout(w35), .Result(w36)); //: @(270, 500) /sz:(202, 74) /sn:0 /p:[ Ti0>5 Ti1>0 Ti2>9 Ti3>11 Li0>1 Li1>1 Li2>0 Bo0<0 Ro0<1 ] //: LED g19 (w22) @(523,612) /sn:0 /w:[ 0 ] /type:0 //: SWITCH g6 (w12) @(216,47) /sn:0 /w:[ 0 ] /st:0 /dn:1 //: LED g7 (w8) @(379,141) /sn:0 /w:[ 0 ] /type:0 //: DIP g9 (w30) @(317,32) /sn:0 /w:[ 0 ] /st:0 /dn:1 //: DIP Operation (w17) @(499,453) /w:[ 7 ] /st:1 /dn:0 ALUA g15 (.ainvert(w24), .binvert(w14), .Operation(w17), .Cin(w21), .b(w26), .a(w25), .Cout(w13), .Result(w28)); //: @(266, 690) /sz:(198, 74) /sn:0 /p:[ Ti0>11 Ti1>3 Ti2>13 Ti3>1 Li0>0 Li1>0 Bo0<1 Ro0<1 ] //: LED g20 (w36) @(527,528) /sn:0 /w:[ 0 ] /type:0 //: SWITCH Carry_In (w5) @(340,450) /w:[ 1 ] /st:0 /dn:0 //: LED g17 (w29) @(523,762) /sn:0 /w:[ 0 ] /type:0 assign {w32, w26, w20, w10} = w18; //: CONCAT g29 @(139,807) /sn:0 /R:2 /w:[ 0 1 1 1 0 ] /dr:0 /tp:0 /drp:0 //: SWITCH B_Invert (w14) @(192,450) /w:[ 13 ] /st:0 /dn:0 //: joint g5 (w17) @(499, 482) /w:[ -1 6 8 5 ] ALUA g14 (.ainvert(w24), .binvert(w14), .Operation(w17), .Cin(w35), .b(w20), .a(w19), .Cout(w21), .Result(w22)); //: @(266, 596) /sz:(198, 74) /sn:0 /p:[ Ti0>0 Ti1>7 Ti2>11 Ti3>1 Li0>0 Li1>0 Bo0<0 Ro0<1 ] //: SWITCH A_invert (w24) @(194,496) /w:[ 7 ] /st:0 /dn:0 //: LED g21 (w23) @(518,872) /sn:0 /w:[ 0 ] /type:0 //: joint g24 (w17) @(499, 585) /w:[ -1 4 10 3 ] ALUB g23 (.ainvert(w24), .Cin(w13), .Operation(w17), .binvert(w14), .a(w31), .b(w32), .Cout(w23), .set(w37), .Result(w29)); //: @(256, 792) /sz:(204, 84) /sn:0 /p:[ Ti0>13 Ti1>0 Ti2>0 Ti3>0 Li0>0 Li1>1 Bo0<1 Ro0<0 Ro1<1 ] //: joint g22 (w24) @(230, 483) /w:[ 4 -1 6 3 ] //: joint g26 (w24) @(230, 592) /w:[ 1 2 -1 8 ] ALUA g0 (.ainvert(w3), .binvert(w9), .Operation(w30), .Cin(w12), .b(w1), .a(w11), .Cout(w7), .Result(w8)); //: @(131, 138) /sz:(198, 74) /sn:0 /p:[ Ti0>0 Ti1>1 Ti2>1 Ti3>1 Li0>0 Li1>0 Bo0<1 Ro0<1 ] //: joint g12 (w14) @(249, 674) /w:[ 2 4 -1 1 ] //: LED g18 (w28) @(523,688) /sn:0 /w:[ 0 ] /type:0 assign {w31, w25, w19, w6} = w0; //: CONCAT g30 @(145,619) /sn:0 /R:2 /w:[ 1 1 1 0 1 ] /dr:0 /tp:0 /drp:0 endmodule //: /netlistEnd //: /netlistBegin ALUB module ALUB(Result, Operation, Cin, b, ainvert, Cout, set, a, binvert); //: interface /sz:(135, 68) /bd:[ Ti0>binvert(26/135) Ti1>Operation[1:0](106/135) Ti2>Cin(54/135) Li0>b(45/68) Li1>a(16/68) Bo00 Li0>9 Li1>3 Bo0<1 Ro0<0 ] _GGMUX2 #(8, 10) g9 (.I0(a), .I1(~a), .S(ainvert), .Z(w2)); //: @(179,163) /sn:0 /R:1 /w:[ 0 3 0 0 ] /ss:0 /do:0 _GGAND2 #(6) g7 (.I0(w2), .I1(w1), .Z(w5)); //: @(296,166) /sn:0 /w:[ 3 9 1 ] //: IN g20 (ainvert) @(160,218) /sn:0 /w:[ 1 ] _GGMUX2 #(8, 10) g15 (.I0(b), .I1(~b), .S(binvert), .Z(w1)); //: @(188,294) /sn:0 /R:1 /w:[ 0 3 1 0 ] /ss:0 /do:0 //: joint g17 (b) @(138, 304) /w:[ 1 2 4 -1 ] //: OUT g5 (Cout) @(310,340) /sn:0 /w:[ 0 ] //: GROUND g14 (w0) @(370,247) /sn:0 /w:[ 0 ] //: OUT g21 (set) @(399,333) /sn:0 /w:[ 5 ] //: joint g22 (set) @(352, 278) /w:[ -1 2 1 4 ] //: IN g0 (a) @(122,173) /sn:0 /w:[ 5 ] //: joint g18 (w2) @(213, 163) /w:[ 2 -1 1 4 ] //: IN g12 (binvert) @(152,347) /sn:0 /w:[ 0 ] endmodule //: /netlistEnd //: /netlistBegin ALU0 module ALU0(Result, Operation, Cin, b, less, ainvert, Cout, a, binvert); //: interface /sz:(135, 68) /bd:[ Ti0>binvert(26/135) Ti1>Operation[1:0](106/135) Ti2>Cin(54/135) Li0>b(45/68) Li1>a(16/68) Bo00 Li0>9 Li1>3 Bo0<1 Ro0<0 ] //: IN g9 (less) @(362,232) /sn:0 /w:[ 0 ] _GGAND2 #(6) g7 (.I0(w3), .I1(w1), .Z(w5)); //: @(294,144) /sn:0 /w:[ 3 9 1 ] //: joint g20 (a) @(122, 151) /w:[ 2 4 1 -1 ] _GGMUX2 #(8, 10) g15 (.I0(b), .I1(~b), .S(binvert), .Z(w1)); //: @(153,294) /sn:0 /R:1 /w:[ 0 3 1 0 ] /ss:0 /do:0 //: joint g17 (b) @(103, 304) /w:[ 1 2 4 -1 ] //: IN g14 (ainvert) @(138,186) /sn:0 /w:[ 0 ] //: OUT g5 (Cout) @(290,336) /sn:0 /w:[ 0 ] //: IN g0 (a) @(94,151) /sn:0 /w:[ 0 ] _GGMUX2 #(8, 10) g18 (.I0(a), .I1(~a), .S(ainvert), .Z(w3)); //: @(157,141) /sn:0 /R:1 /w:[ 3 5 1 0 ] /ss:0 /do:0 //: IN g12 (binvert) @(117,347) /sn:0 /w:[ 0 ] endmodule //: /netlistEnd //: /netlistBegin ALUA module ALUA(Result, Operation, Cin, b, ainvert, Cout, a, binvert); //: interface /sz:(198, 74) /bd:[ Ti0>Cin(112/198) Ti1>Operation[1:0](166/198) Ti2>binvert(75/198) Ti3>ainvert(26/198) Li0>a(17/68) Li1>b(45/68) Bo00 Li0>9 Li1>3 Bo0<1 Ro0<0 ] //: IN g9 (ainvert) @(96,207) /sn:0 /w:[ 0 ] _GGAND2 #(6) g7 (.I0(w2), .I1(w1), .Z(w5)); //: @(294,144) /sn:0 /w:[ 3 9 1 ] //: joint g20 (a) @(106, 151) /w:[ 2 4 1 -1 ] _GGMUX2 #(8, 10) g15 (.I0(b), .I1(~b), .S(binvert), .Z(w1)); //: @(153,294) /sn:0 /R:1 /w:[ 0 3 1 0 ] /ss:0 /do:0 //: joint g17 (b) @(103, 304) /w:[ 1 2 4 -1 ] //: OUT g5 (Cout) @(300,359) /sn:0 /w:[ 0 ] //: GROUND g14 (w0) @(371,282) /sn:0 /w:[ 0 ] //: IN g0 (a) @(78,151) /sn:0 /w:[ 0 ] _GGMUX2 #(8, 10) g18 (.I0(a), .I1(~a), .S(ainvert), .Z(w2)); //: @(145,141) /sn:0 /R:1 /w:[ 3 5 1 0 ] /ss:0 /do:0 //: IN g12 (binvert) @(117,347) /sn:0 /w:[ 0 ] endmodule //: /netlistEnd //: /netlistBegin FA module FA(b, a, Sum, Cout, Cin); //: interface /sz:(70, 61) /bd:[ Ti0>Cin(31/70) Li0>a(8/61) Li1>b(38/61) Bo0