//: version "2.0-b10"
//: property encoding = "iso8859-1"
//: property locale = "en"
//: property prefix = "_GG"
//: property title = "PANIC.v"
//: property timingViolationMode = 2
//: property initTime = "0 ns"

`timescale 1ns/1ns

//: /netlistBegin main
module main;    //: root_module
reg [1:0] w0;    //: /sn:0 {0}(285,234)(262,234)(#:262,204)(#:232,204){1}
reg w8;    //: /sn:0 {0}(327,191)(347,191)(347,213){1}
reg Reset;    //: {0}(337,360)(50:352,360)(352,327){1}
reg [7:0] w11;    //: /sn:0 {0}(285,307)(262,307)(#:262,348)(#:232,348){1}
reg [1:0] w10;    //: /sn:0 {0}(285,284)(262,284)(262,297)(#:232,297){1}
reg [1:0] w5;    //: /sn:0 {0}(285,256)(262,256)(#:262,251)(#:232,251){1}
wire [7:0] w6;    //: /sn:0 {0}(#:507,190)(507,264)(412,264){1}
wire [7:0] w7;    //: /sn:0 {0}(#:438,190)(438,236)(412,236){1}
//: enddecls

  //: DIP Rdest (w10) @(194,297) /R:1 /w:[ 1 ] /st:2 /dn:1
  //: DIP Data (w11) @(194,348) /R:1 /w:[ 1 ] /st:4 /dn:1
  //: LED RO1 (w7) @(438,183) /w:[ 0 ] /type:3
  //: SWITCH g2 (Reset) @(320,360) /sn:0 /w:[ 0 ] /st:0 /dn:1
  RF g1 (.RegWrite(w8), .Data(w11), .Rdest(w10), .RS1(w0), .RS2(w5), .reset(Reset), .RO1(w7), .RO2(w6));   //: @(286, 214) /sz:(125, 112) /sn:0 /p:[ Ti0>1 Li0>0 Li1>0 Li2>0 Li3>0 Bi0>1 Ro0<1 Ro1<1 ]
  //: DIP RS2 (w5) @(194,251) /R:1 /w:[ 1 ] /st:2 /dn:1
  //: LED RO2 (w6) @(507,183) /w:[ 0 ] /type:3
  //: DIP RS1 (w0) @(194,204) /R:1 /w:[ 1 ] /st:1 /dn:1
  //: SWITCH RegWrite (w8) @(310,191) /w:[ 0 ] /st:0 /dn:1

endmodule
//: /netlistEnd

//: /netlistBegin RF
module RF(RegWrite, Data, Rdest, RS2, RO2, reset, RO1, RS1);
//: interface  /sz:(125, 112) /bd:[ Ti0>RegWrite(61/125) Li0>RS2[1:0](42/112) Li1>RS1[1:0](20/112) Li2>Rdest[1:0](70/112) Li3>Data[7:0](93/112) Bi0>reset(66/125) Ro0<RO2[7:0](50/112) Ro1<RO1[7:0](22/112) ] /pd: 1 /pi: 1 /pe: 1 /pp: 1
//: property prot_data=1
//: property prot_intf=1
input [1:0] Rdest;    //: /sn:0 {0}(175,230)(#:138,230){1}
input [7:0] Data;    //: /sn:0 {0}(#:199,129)(245,129){1}
//: {2}(249,129)(302,129)(302,138){3}
//: {4}(247,131)(247,181){5}
//: {6}(#:249,183)(302,183)(302,193){7}
//: {8}(247,185)(247,239){9}
//: {10}(#:249,241)(302,241)(302,253){11}
//: {12}(247,243)(247,309)(302,309)(302,321){13}
output [7:0] RO1;    //: /sn:0 {0}(571,190)(#:541,190){1}
input [1:0] RS2;    //: /sn:0 {0}(#:512,382)(530,382)(530,353){1}
output [7:0] RO2;    //: /sn:0 {0}(573,330)(#:543,330){1}
supply0 w2;    //: /sn:0 {0}(265,331)(259,331)(259,349){1}
input [1:0] RS1;    //: /sn:0 {0}(#:504,259)(528,259)(528,213){1}
supply0 w5;    //: /sn:0 {0}(383,382)(383,338){1}
//: {2}(383,334)(383,270){3}
//: {4}(383,266)(383,210){5}
//: {6}(383,206)(383,153)(341,153){7}
//: {8}(381,208)(341,208){9}
//: {10}(381,268)(341,268){11}
//: {12}(381,336)(341,336){13}
input RegWrite;    //: /sn:0 {0}(165,288)(188,288)(188,252){1}
input reset;    //: /sn:0 {0}(315,379)(272,379){1}
wire w14;    //: /sn:0 {0}(265,263)(226,263)(226,236)(204,236){1}
wire w4;    //: /sn:0 {0}(265,148)(219,148)(219,212)(204,212){1}
wire [7:0] w15;    //: /sn:0 {0}(#:302,342)(302,348)(463,348){1}
//: {2}(467,348)(514,348){3}
//: {4}(#:465,346)(465,208)(512,208){5}
wire w19;    //: /sn:0 {0}(204,248)(215,248)(215,275){1}
wire [7:0] w0;    //: /sn:0 {0}(#:302,159)(302,172)(406,172){1}
//: {2}(410,172)(#:512,172){3}
//: {4}(408,174)(408,312)(514,312){5}
wire w3;    //: /sn:0 {0}(331,379)(371,379)(371,328){1}
//: {2}(371,324)(371,260){3}
//: {4}(371,256)(371,200){5}
//: {6}(371,196)(371,143)(341,143){7}
//: {8}(369,198)(341,198){9}
//: {10}(369,258)(341,258){11}
//: {12}(369,326)(341,326){13}
wire [7:0] w21;    //: /sn:0 {0}(#:302,274)(302,297)(443,297){1}
//: {2}(445,295)(445,196)(#:512,196){3}
//: {4}(445,299)(445,336)(514,336){5}
wire [7:0] w28;    //: /sn:0 {0}(#:302,214)(302,230)(423,230){1}
//: {2}(425,228)(425,184)(#:512,184){3}
//: {4}(425,232)(425,324)(514,324){5}
wire w9;    //: /sn:0 {0}(265,203)(227,203)(227,224)(204,224){1}
//: enddecls

  //: IN g4 (RegWrite) @(163,288) /sn:0 /w:[ 0 ]
  _GGREG8 #(10, 10, 20) g8 (.Q(w0), .D(Data), .EN(w5), .CLR(w3), .CK(w4));   //: @(302,148) /sn:0 /w:[ 0 3 7 7 0 ]
  //: IN g3 (Data) @(197,129) /sn:0 /w:[ 0 ]
  _GGMUX4x8 #(12, 12) g13 (.I0(w15), .I1(w21), .I2(w28), .I3(w0), .S(RS2), .Z(RO2));   //: @(530,330) /sn:0 /R:1 /w:[ 3 5 5 5 1 1 ] /ss:0 /do:0
  //: IN g2 (Rdest) @(136,230) /sn:0 /w:[ 1 ]
  //: IN g1 (RS2) @(510,382) /sn:0 /w:[ 0 ]
  //: joint g16 (w28) @(425, 230) /w:[ -1 2 1 4 ]
  _GGREG8 #(10, 10, 20) g11 (.Q(w15), .D(Data), .EN(w5), .CLR(w3), .CK(w2));   //: @(302,331) /sn:0 /w:[ 0 13 13 13 0 ]
  //: joint g28 (Data) @(247, 183) /w:[ 6 5 -1 8 ]
  _GGREG8 #(10, 10, 20) g10 (.Q(w21), .D(Data), .EN(w5), .CLR(w3), .CK(w14));   //: @(302,263) /sn:0 /w:[ 0 11 11 11 0 ]
  //: joint g27 (Data) @(247, 241) /w:[ 10 9 -1 12 ]
  //: joint g19 (w5) @(383, 208) /w:[ -1 6 8 5 ]
  //: OUT g6 (RO2) @(570,330) /sn:0 /w:[ 0 ]
  //: IN g7 (reset) @(270,379) /sn:0 /w:[ 1 ]
  _GGREG8 #(10, 10, 20) g9 (.Q(w28), .D(Data), .EN(w5), .CLR(w3), .CK(w9));   //: @(302,203) /sn:0 /w:[ 0 7 9 9 0 ]
  //: LED g31 (w19) @(215,282) /sn:0 /R:2 /w:[ 1 ] /type:0
  //: joint g20 (w5) @(383, 268) /w:[ -1 4 10 3 ]
  //: joint g15 (w21) @(445, 297) /w:[ -1 2 1 4 ]
  _GGDECODER4 #(6, 6) g29 (.I(Rdest), .E(RegWrite), .Z0(w19), .Z1(w14), .Z2(w9), .Z3(w4));   //: @(188,230) /sn:0 /R:1 /w:[ 0 1 0 1 1 1 ] /ss:0 /do:0
  //: joint g25 (w3) @(371, 326) /w:[ -1 2 12 1 ]
  //: joint g17 (w0) @(408, 172) /w:[ 2 -1 1 4 ]
  //: OUT g5 (RO1) @(568,190) /sn:0 /w:[ 0 ]
  //: joint g14 (w15) @(465, 348) /w:[ 2 4 1 -1 ]
  //: joint g24 (w3) @(371, 258) /w:[ -1 4 10 3 ]
  //: joint g21 (w5) @(383, 336) /w:[ -1 2 12 1 ]
  //: joint g23 (w3) @(371, 198) /w:[ -1 6 8 5 ]
  //: joint g26 (Data) @(247, 129) /w:[ 2 -1 1 4 ]
  _GGNBUF #(2) g22 (.I(reset), .Z(w3));   //: @(321,379) /sn:0 /w:[ 0 0 ]
  //: IN g0 (RS1) @(502,259) /sn:0 /w:[ 0 ]
  //: GROUND g18 (w5) @(383,388) /sn:0 /w:[ 0 ]
  _GGMUX4x8 #(12, 12) g12 (.I0(w15), .I1(w21), .I2(w28), .I3(w0), .S(RS1), .Z(RO1));   //: @(528,190) /sn:0 /R:1 /w:[ 5 3 3 3 1 1 ] /ss:0 /do:0
  //: GROUND g30 (w2) @(259,355) /sn:0 /w:[ 1 ]

endmodule
//: /netlistEnd