Assembly Language Overview
- We have seen that we can simplify the instruction set, and perhaps
- Speed up fetch
- Speed up instruction Execution
- Keep memory references close to constant
- Need more instructions to accomplish the same task
- Terms RISC, CISC, Load/Store instruction set
- We will see in chapter 9 how all this can be used to make a pipeline
- A few more details about instruction sets from chapter 4.
- Branch instructions
- Unconditional, conditional
- We can do conditional branches several ways:
- Each branch has a condition
- Conditions include, gt, ge, lt, le, z, nz,
- Plus overflow, and other exceptions
- BR## R1 R2 dest
- BR## R1 dest
- The dest is an offset from the current PC
- Assume we have a 32 bit instruction.
- Assume we need n bits for the opcode
- We need 5 bits for each register
- How many bits does each leave for destination addresses?
- Unconditional branches represent a problem too
- jump address
- We would like to be able to address all 232 bits of
memory.
- But if we use n bits for an opcode, we only get 232-n addresses.
- sethi imm
- Set top 22 bits of a number
- Clear the low 10 bits to be zero
- Immedately followed by an or, will set all 32 bits to an address
- jump register
- branch address
- Sparc assembly
- Three types of instructions
- R type
- Call
- Jump
- This gives us the ability to maximize use of the instruction field
- While keeping everything in 32 bits.
- use 2 bits to identify instruction class.
- For call there is only one instruction, so it is completely
identified.
- For branch we have two classes
- Branch (or jump)
- SETHI
- We need a condition for the branch
- Or we need a register destination for the sethi
- 22 bits, that get sign extended for the displacement
- For R-type
- More complex here
- Three sub classes, R-R, R-I, FP
- Include a 6 bit additional instruction opcode field
- Plus source and destination registers
- And optional other fields.
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- We skipped some terms
- Load delay slot
- Branch delay slot
- We will get to them.