Pipelines Continued (Stalls and Hazards)

• A stall occurs when a stage of the pipeline can not be completed in a single clock cycle for some reason.
• A cache miss can cause a pipeline stall.
• Loads and Stores are likely to cause stalls.
• But they are not the only souce.
• Three other causes of stalls
  • Data Hazards - Register Interlock
  • Structural Hazards - Poor design of the machine,
    • Pc uses the ALU for incrementing
    • But ALU is needed for an add too.
    • These can be designed away.
    • Just need more hardware (transistors)
  • Control Hazards - Due to jumps, branches or calls.
    • This is a real problem
    • No complete solution exits.
• Data Hazards:
  • Consider the following code:

    add R5, R4, R3   ; R5<- R4+R3
    add R6, R5, R2   ; R6<- R6+R3
           

  • It will produce the folowing timing diagram

    Time	Fetch	Decode	ALU	Store
    t0	add R5,R4,R3
    t1	add R6,R5,R2	add R5,R4,R3
    t2		add R6,R5,R2	add R5,R4,R3
    t3			add R6,R5,R2	add R5,R4,R3

  • Notice, in this case, the second add needs the results before they are stored by the first.
  • This is called a RAW (Read After Write) hazard, or write/read dependancy.
  • We could also have WAR, (Write after Read) and WAW (Write after Write)
  • As the pipeline becomes longer, more of these type occur.
  • Detection is not too bad:
    • Every time a register is a destination,
    • Set a bit marking it as "dirty"
    • Clear the bit when we save a new value.
  • This can be fixed by register interlock:
    • Detect the problem
    • Block the pipe behind the problem
    • Ie stall the second instruction causing the problem.
    • This is bad, it decreases our throughput.
  • This can be fixed by register forwarding:
    • Detect if a value needed in ahead of us in the pipeline
    • Add special hardware to send this back down the pipeline.
    • 
  • Notice that we will have the same problem if we are using a coprosser.
• Branches and Branch Hazards
  • To nullify an instruction:
    • Simply change the control signals before the cc is set, or any writing (memory or registers) is done.
    • But what about this example:

             sub  R0, R4, R5
             breq dest
             bds
             ...
      dest:  op3
      	  

    • assume R4=R5
    • This table should summarize the operation:

      Time	Fetch	Decode	ALU	Store
      t0	add R0,R4,R5
      t1	breq dest	add R0,R4,R5
      t2	bds	breq dest	add R0,R4,R5
      t3	op3	bds	breq dest	add R0,R4,R5