Instruction Interpretation

• In this chapter, we will take a look at some advanced topics
  • An implementation of a Load/Store Risc Machine
  • Instructions/Memory optimizations (prefetch, + )
  • Pipelining
  • Superpipelinging and superscalar
  • Microprogramming
• A new simple machine
  • 16 bit word
  • 16 GP Registers, R0-R15
  • R0 is always 0, as in the Sparc
  • Three Instruction Formats
    • Data Manipulation (R-type)
      • Add, MPY, ...
      • 4 bit opcode
      • 3 4 bit registers
      • oooodddd11112222 (1 = s1, 2 = s2)
      • op dest src1 src2
      • Each of these instructions sets the Z,N bits in a condition register.
    • Data Transfer (R-type)
      • 4 bit opcode
      • Destination
      • Source1, Source2
      • LDW R_d R_s1 R_s2
      • R[dest] = M[R[s1] + R[s2]]
      • Notice this gives us a full 16 bit address space.
      • Or if We only load bytes, we can go on byte boundries.
      • So we can address 2¹⁶ bytes of memory
      • LDW, STW
      • Byte operations (LDB, STB) work on lower 8 bits of a register
      • Sign extend on load.

    • Pseudo Code	Op Code	Pseudo Code	Op Code
      LDW	0000	LDB	0001
      STW	0010	STB	0011
      ADD	0100	SUB	0101
      AND	0110	OR	0111
      XOR	1000	XORN	1001

    • Two set register operations (S-type)
      • SETHI R_d imm
      • SETLO R_d imm
      • 8 bit immediate
      • Sets the top or bottom 8 bits of the register.

      • Pseudo Code	Op Code	Pseudo Code	Op Code
        SETHI	1010	SETLO	1011

    • Branch (J-type)
      • 5 bit opcode
      • 11 bit address
      • PC=PC+addr*2
      • (Byte addressable, so instructions must be word alligned)

      • Pseudo Code	Op Code	Pseudo Code	Op Code
        BRA	11000	BREQ	11001
        BRNE	11010	BRLT	11011
        BRLE	11100	BRGT	11101
        BRGE	11110

  • We will use three internal busses
  • An ALU, and a shifter.
  • 
  • Sz is a memory size selector, 0 = byte, 1=word
  • MS is memory select
  • R/W is Read not Write
  • Trace Instruction Fetch
  • Trace ADD R5, R3, R2 (R5 <- R3+R2)
  • Trace LW R4, R2, R3 (R4 <- M[R2+R3]
  • Trace SETHI R4, 0
  • Trace BEQ 100
  • There is a fetch operation.
  • There will be four paths in our state table for this machine:
    • Data Migration
      • Load or Store
    • Data Manipulation
      • ALU, Shift, ...
    • Register Set
      • SETHI, SETLO
    • Branch