• Bit Mainuplation
    • Bitwise Operations - work on an entire register
      • AND Rd Rs1 Rs2
      • OR Rd Rs1 Rs2
      • XOR Rd Rs1 Rs2
      • ANDN Rd Rs1 Rs2 (Rd = Rs1 + ! Rs2)
      • ORN Rd Rs1 Rs2 (Rd = Rs1 * ! Rs2)
      • A mask is used to select a portion of a bit string
        • Assume 8 bit registers
        • AND R1 R4 #128 to zero out everything but the top bit
        • OR R3 R2 #128 sets the top bit in R3
    • Direct Bit Access
      • BB Rs n target - branch to target if bit n is set in Rs
      • BSET Rd n m - sets bits n through m in Rd to be 1
      • BCLR Rd n m - sets bits n through m in Rd to be 0
    • Shift and Rotate
      • SLZ Rd Rs n - shift left fill with 0
      • SL0 Rd Rs n - shift left fill with 1
      • ROTL Rd Rs n - rotate left.
  • The SPARC processor Instruction Encoding
    • SPARC- Scalable Processor Architecture
    • Based on the RISC I and RISC II processors developed at UC Berkeley
    • This is an open architecture
    • A brief timeline:
      • Late Mid 80's - Motorola 68000 based SUN3 machines
      • 87 - First SPARC based machine, the SUN-4
      • 89 - SPARCstation 1, 12.5 MIPS
      • 90 - SPARCstation II
    • Hardware Overview
      • There are 32, 32 bit general purpose registers
      • Memory addresses are 32 bits long
      • Instructions are 32 bits long and aligned on word boundries.
      • A condition code register has four bits, zero, negative, overflow, and carry
      • The processor includes a branch delay slot
    • Instruction Format
      • General
        • op, op2, op3, opf - operation code
        • rd - destination register
        • rs1, rs2 - source registers
        • i - immediate
        • asi - address space identifier
        • simm13 - 13 bit signed immediate value
        • Operations are supported on half, full and double words
        • Double word operations use two registers, and must start with an even register, ie R2, R3 but not R3, R4
        • Halfword operations must include signed or unsigned
        • Load and store operations use the first two variations of the above.
        • All this is encoded in the op and op3 bits
        • More about this in the next chapter
        • Data manipulation
          • Use all three forms
          • Floating point uses third
          • simm13 field is extended to 32 bits
      • CALL
        • disp30 - 30 bit displacement
        • The top 30 bits only are encoded since instructions are on full word (4 byte) boundries, the last two bits are 00
      • SETHI/Branch
        • a - nullification bit
        • cond - condition for branch
        • disp22 - 22 bit displacement
        • imm22 - 22 bit immediate value
        • for branch imm22<<2+00, extend sign, add to pc
        • SETHI
          • Sets the 22 high bits of Rd
          • Clears the 10 low order bits of Rd
          • This is the way to deal with all 32 bits in a register
          • For a call.