Chapter 4, Part 2, Registers

• So now we get to the part that has been bugging you
• What about registers?
• We already discussed that they are MUCH faster than memory
• Let's rewrite our example code to use registers
  • Three address machine

  • mpy R2, 100, 104
    mpy R3, 108, 112
    mpy R3, R3, 116
    Add 100, R2, R3
           

  • Notice that this only takes 10 memory accesses

  • Two Address Machine

  • mpy 100, 104 ; 4 accesses
    load R3, 108
    mpy R3, 112
    mpy R3, 116
    add 100, R3
           

  • Notice, this takes 13 memory accesses

  • Some machines require a register as one argument, these are 1-1/2 address machines.

  • load R2, 100
    mpy  R2, 104
    load R3, 108
    mpy  R3, 112
    mpy  R2, 116
    add  R2, R3
    store 100, R2
    	

  • This requires 13 memory access as well.
• Load Store
  • Change the rules, only operations that are allowed to access memoy are
    • load register adddress
    • store address, register
  • All other instructions are register - register only

  • load R2, 100
    load R3, 104
    mpy  R2, R2, R3
    load R3, 108
    load R4, 112
    load R5, 116
    mpy R3, R3, R4
    mpy R3, R3, R5
    add R2, R2, R3
    store 100 R2
          

  • There are 16 memory accesses here.
  • This type of architecture is called LOAD/STORE
  • However, we can rearrange our code so that some of the instructions can proceed in parallel (but more of that in Arch II)
  • This is called instruction overlapping
  • This somewhat hides the memory latency
  • some hardware, and most compilers will rearrange the instructions to take advantage of this idea.
  • some machines require an operation between a load and when the value is used. (load delay slot)
  • If we have 32 registers, how many bits do we need to encode them?
  • Part of the RISC removal of instructions include
    • R0 is unusable, but is a source of 0
    • ADD RN, RM, R0 is the same as COPY RN, RM so there is no copy instruction.
    • SUB RN, R0, RN is the same as NEGATE RN, so there is no negation operation.
    • ADD RN, R0, R0 is the same as CLEAR RN, so there is not one.
    • some assemblers provide pseudo-ops for these instructions

• Different instructions are provided to load a byte, halfword and word
  • load.b R2, 24 ; loads byte at 24 into register 2
  • load.h R2, 24; Loads two bytes starting at 24 into R2
  • load.w R2, 24;

• Immediates (constants) start with a # and sometimes have their own instructions
• loadi R3, #4; R3 = 4;
• load R3, #4;