Some odds and ends

• Time
  • 1x10³ miliseconds (ms) = 1 second
  • 1x10⁶ microseconds (us) = 1 second
  • 1x10⁹ nanoseconds (ns) = 1 second
  • 1x10¹² picoseconds (ps) = 1 second
• Frequency is in units/timeperiod
  • Hertz = is cycles per second
  • A 1 MHz clock runs at 1,000,000 = 1 x 10 ⁶ cycles/second
  • The peroid of a wave is how long it takes for a single cycle
  • Period is timeperiod/unit
  • Period = 1/Frequency
• So a clock running at 1MHz has a period of
  • 1x10⁶ cycles/second
  • 1 second/1x10⁶ cycles = 1x10^-6 seconds/cycle
  • 1x10^-6seconds/cycle x 1x10⁹ns/second = 1x10³ ns/cycle
• And a clock running at 100MHz has a period of
  • 100 x 10 ⁶ cycles/second
  • 1 second / 100x10⁶ cycles = 1 x 10 ^-8 seconds/cycle
  • 1 x 10 ^-8 seconds/cycle x 1x10⁹ns/sec = 1x10¹ ns/cycle = 10ns/cycle
• If our clock requires 50ns/cycle
  • 1 cycle / 50 ns x 1 x 10 ⁹ ns/second = .2 x 10⁸ cycles/second = 2x10⁷ cycles/second = 20 MHz
• If we require 2 clock cycles to complete an instruction
  • 1 instruction / 2 cycles x 2x 10⁷ cycles/second = 1x10⁷ instructions/ second or 10 Million Instructions/second.

• For a bus
  • We would like to count how much we are delaying due to the bus
  • Transaction Access Time is the time it takes for the slave from when it sees the transaction line is lit until it asserts the done signal.
  • The Transactoin Access Time for memory is 80 ns (or 10 depending on the memory)
  • Transaction Access Time is determined by the folowing factors:
    • The time for the bus to stabalize (s ns)
    • We need 1s for the address to stabalize
    • We need another for the start signal to stabalize
    • We need to have the answer done s before the end of the down stroke of the second clock pulse.
    • This whole action should take place within 1.5 clock pulses
    • (cp*1.5 - 3*s)
    • We might need to stall w clock pulses
    • So our total time a <= (cp* w) - cp*1.5-3s
    • If we solve for w we get
    • w >= (a - 1.5*cp + 3 *s ) / cp
  • An example:
    • The bus clock is running at 13 MHz
    • 13x10⁶ cycles/second
    • 1/13x10⁶ sec/cycle x 1 x 10 ⁹ = 77 ns/cycle
    • Cycle time is 80 ns
    • 10 ns for bus stabilazation
    • w >= (78-1.5*80+3(10))/80 = -.16
    • w >= 0;
  • If we slow the clock down. to 9MHz
    • 111 ns/cycle
    • w >= .26, w>=1
    • This means we will need an additional wait cycle.
    • Which means the entire transaction will take 3*80 ns or 240 ns for the transaction.