Buses
- We use a bus to transmit data between two things
- An internal bus
- An external bus
- Memory to CPU
- Disk to CPU
- CPU to other devices.
- Internal buses are tightly controlled and are hard to expand.
- External buses rely on self-selection and must be easy to expand.
- The master/slave relationship
- A data transfer is called a bus transaction
- The initiator of a transaction is called the master.
- The other participant in the transaction is called a slave.
- This only lasts for a single transaction.
- In CPU-> Memory, memory is always a slave
- A bus master is any component that can act as a transaction master.
- Buses support
- Read transactions.
- Write transactions.
- These behave much like the memory accesses we have discussed.
- Buses can be Synchronous - with a shared clock
- These tend to be easier to understand but hard to expand
- They are hard to add devices to.
- Or asynchronous
- Can add devices easier
- More tricky to work out.
- Synchronous Bus Protocols
- All items on the bus share a common clock
- Everything must sync to this bus
- A bus has the following lines (some may have multiple wires)
- Start - the master raises this to start a transaction
- Data - The master puts data on for a write, the slave for a read
- Address - The master puts the address on this line
- Read/not Write - The master sets this line
- Done - The slave sets the value of this line when the transaction
is finished
- Clock - The bus provides the signal on this line.
- When the start line is raised
- All devices look at the address lines
- The device who covers that set of addresses becomes the slave
- Both types of transactions take two timing cycles (Clock pulses)
- The clock pulse is determined on how long it takes to transfer data
over the bus.
- We usually have to allow the lines a period to "stabilize"
- A write transaction.
-
- A read transaction
-
- Note the master looks for the done line on the trailing edge of the
clock.
- If the slave cannot service the request in two clock cycles,
the system must enter a wait state for as many cycles as it takes
to complete the request.
- Since we need to wait for the leading edge of a clock pulse to
change states, synchronous buses are slower than asynchronous
- A clock operates in the range from 5 to 50 MHz
- The bandwidth is how much data (bps) can be handled by the system.
- He presents some mathematics on timing, that we will skip. This is
mostly concerned with how a faster clock does not necessarily
make a faster bus.
- Bus Arbitration occurs when there is more than one master.
- This is a protocol that allows multiple masters that want access
to the bus to decide on who has it.