Chapter 3 Part 1 (continued) and Part 2 (CPU)

• Memory
  • We now know how to build a single memory bank.
  • We will need more than one bank of memory to really work
  • A word is somewhat elusive. It is really the number of bits in a register in the architecture.
  • In any case, let us try to build an 16 bit wide memory out of two 8 bit wide memories.
    • We have two 2^n-1 x 8 bit memories.
    • We will look for memory at a global address (2ⁿ bits
    • We will use the LSB in our address to select the memory bank to address.
    • The remaining n-1 bits will select the 8 bits we want.
    • Consider:
    • 
    • The addresses shown are global, each bank has local relative addresses as well.
    • The box (the c shaped thing) is a control component, we could build this? YES!
    • How would we want to store data on in this memory
      • First 2^n-1 bytes in bank 0, second in bank 1
      • Even numbered bits in bank 0,
      • Some other way?
      • It turns out that the second is faster than the first.
      • Why?
      • This is called interleaved addressing
      • Works that way with disks two (Raid level 0)
• Byte Ordering
  • If we have 16 bits in a row, how do we store numbers in them
  • We mostly write, and label things left to right
  • We mostly write numbers right to left (smallest part on the right)
  • Different machines write things in different orders.
  • Just to make things confusing, someone read Gulliver's Travels and there was something about which end of an egg to do something to. We mostly write, and label things left to right
  • We mostly write numbers right to left (smallest part on the right)
  • Different machines write things in different orders.
  • Just to make things confusing, someone read Gulliver's Travels and there was something about which end of an egg to do something to.
  • We generally keep bits within bytes in order (but not always)
  • We might store our bytes left to right or right to left.
    • B₀B₁B₂... (Little Endian)
    • ... B₂B₁B₀ (Big Endian)
    • Word at address F0 - F4, Number A1B2
    • 
    • Both are equally valid, and there is no best solution.
  • If the bits within a byte match byte order, the system is said to be consistent, otherwise it is inconsistent.
  • The x86 chip is consistent little endian (right to left, right to left)
  • Sparc is Consistent Big endian (left to right, left to right)
  • The Motorola 68000 is Inconsistent Big Endian (left to right, right to left)
• Memory usually must be aligned.
  • In our above example, (of memory), what if we had a 16 bit word start on an even address?
  • What about an odd address?
  • The odd address is hard to deal with, so we don't.
  • It would possibly take multiple memory cycles. This is bad.

    Object	Aligned Address	Misaligned
    Byte	0,1,2,3,4,5,6,7	Never
    HalfWord	0,2,4,6	1,3,5,7
    Word	0,4	1,2,3,5,6,7
    Double Word	0	1,2,3,4,5,6,7

  • In the above chart, addresses must be of the form ??????a