Paging

Notes

• Chapter 9.3
• The solution to external fragmentation is paging
  • Break physical memory into frames
  • Break logical memory into pages
  • A frame and a page have the same size.
• The backing store is a location where frames can be written when not in use.
  • Hard drive or other location
• Address computation
  • Assume: 2^{m bytes of memory}
  • And a frame/page size of 2ⁿ, n < m
  • Thus n bits are used to address memory within a page
  • And p = m-n bits are used to address a page.
  • Example
    • m = 9, or 512 bytes of memory (not many)
    • n = 5 or 32 bytes per page.
    • Thus p = 9-5 or 4, 16 pages.
    • In a memory address like 1011 11010
      • 1011 is the page address, or page 11
      • 11010 is the byte within that page or 26

    • Frame: 0 (0000) Real Address 0 - 31 Low Binary: 0000 00000 High Binary: 0000 11111

      Frame: 1 (0001) Real Address 32 - 63 Low Binary: 0001 00000 High Binary: 0001 11111

      Frame: 2 (0010) Real Address 64 - 95 Low Binary: 0010 00000 High Binary: 0010 11111

      Frame: 3 (0011) Real Address 96 - 127 Low Binary: 0011 00000 High Binary: 0011 11111

      ...

      Frame: 14 (1110) Real Address 448 - 479 Low Binary: 1110 00000 High Binary: 1110 11111

      Frame: 15 (1111) Real Address 479 - 512 Low Binary: 1111 00000 High Binary: 1111 11111

• However it is likely that there will be FAR more memory that that allocated to a process.
• So we will build a page table.
  • Continuing the above example, assume that there are 2^t total bytes of memory, m ≤ t.
  • So there are t-n bits to address pages, or 2^t-n frames.
  • A process does not "see" all of these, only the 2^m-n pages it thinks it has.
  • So we can build a table of size 2^m-n, all the pages that the process thinks it has,
  • But the entry will not be m-n bits, but t-n bits.
  • Continuing the above example
    • Memory size 12 bit addressable,
      • t = 12, or 2² = 4096 bytes.
    • Process memory size, 9 bit addressable
      • m = 9 or 2⁹ = 512 bytes
      • So there are 12-9 or 3 bits left over.
      • If all processes use the same memory, there is room for 2³ or 8 processes in memory.
      • So logical addresses will be 9 bits, but physical addresses 12 bits.
    • Page size, 4 bit or 2⁴ = 16 pages as above.
      • Thus the logical address will be split into 5 bits to address inside a page
      • 4 bits to address the page.
      • So the page table will be 16 entries, but each will hold 4 + 3 bits
      • The Page Table

        Page Number	Page Location
        0000 (0)	001 0111 (23)
        0001 (0)	000 0100 (4)
        0010 (0)	000 0001 (1)
        0011 (0)	001 0000 (16)
        ...	...
        1111 (15)	000 0111 (7)

      • So an address of 0000 10110 would map to 001 0111 10110
    • The page table
      • is per process
      • Allows pages to be "out of order" in memory.
      • Or even not present in memory.
    • Generally there is some hardware to support paging
      • A page table base register(PTBR) points to the location of the page table in memory.
        • The page table is kept in kernel memory
        • And the PTBR points to this memory
        • This keeps the page table from being written/read at context switch time.
      • The PTBR means two memory lookups
        • One for the page table
        • One for the actual memory
        • This can be slow
      • So it is common to implement a translation look-aside buffer (TLB)
        • This is a small set of registers that hold page table information
        • A mapping between page number and frame number
        • Acts as a fully associative cache
        • If a lookup fails in the TLB, it goes to the cache table.
        • See Figure 9.12 on page 367