| Signal | Effect when deasserted | Effect when asserted |
| Reg2Loc | Register comes from Rm field 20:16 | Register comes from Rt field 4:0 |
| RegWrite | None | The register on the Write register input is written with the value of the Write data input |
| ALUSrc | The second ALU operand comes from the second register file output (Read data 2) | The second ALU operand is sign-extended, lower 16 bits of the instruction |
| PCSrc | The PC is replaced by the output of the adder that computes the value of PC+4 | The PC is replaced by the output of the adder that computes the branch target |
| MemRead | NONE | Data memory contents designated by the address input are put on the Read data output |
| MemWrite | NONE | Data memory contents designed by the address input are replaced with the value on the Write data input |
| MemToReg | The value fed into the register Write data input comes from the ALU | The value fed into the register Write data input comes from the data memory |