Data Transfer

Notes

• This continues chapter 2, we are focusing on LEG8
• Looking at page 64, we have a few choices for loading from memory
  • LDUR - load double word from memory
  • LDURSW - load word from memory (signed)
  • LDURH - load half word
  • LDURB - load byte
• If you note, there are corresponding store instructions
• These are mostly (or perhaps exclusively) the only memory access instructions.
• LD* rd, [rs, imm]
• Note on page 64 that these are all in the form Rd = Memory[Rs + imm]
• If we look at the green card, we see that these are all D type instructions

  • Bits	Use
    31-21	Opcode
    20-12	DT Address
    11-10	op2
    9-5	rd
    0-4	rt

  • Note the immediate (DT Address) is signed, so the offset can be either above or below the register.
  • Note the immediate is 9 bits, so -2⁸ to 2⁸-1 (-256 to 255) offset from the register address.
  • Let's revisit the argument about register size and bits in the instruction.
• Let's encode ldur x9, [x22, #64]
  • As noted on the green card (and above), this is a D type instruction
  • There are 11 bits allocated to the op code
    • Looking at the green card, the op code is 7c2₁₆
    • or 0111 1100 0010₂
  • There are 9 bits to the address or immediate field
    • This is two's complement, but 64 is positive
    • 001000000₂
  • The op2 field is set to 00
    • For some D-type instructions we will need to supplement the opcode
    • I am taking on faith that we will pick this up later.
  • Rn is the 5 bits to address the base register
    • x22 or 10110₂
  • Rt is the 5 bits to address the destination register
    • x9 is 01001₂
  • So the entire instruction is

    •     op        imm     op  rn     rt
      11111000010 001000000 00 10110  01001
      1111 1000 0100 0100 0000 0010 1100 1001
       f    8    4    4    0    2    a     9 

  • Ummm, Yes, I do expect you to be able to do this for limited instructions.
  • Why?
    • To annoy Connor
    • We will need it when we trace the data and control paths.
    • We should have a basic understanding of the relationship between assembly and machine language.
    • We need to appreciate how the designers have packed information into 32 bits.
• In the same section they assemble several other instructions
  • addi x9, x9, #1
    • This is an I-type instruction (why?)
    • Describe the format of an I-type (where will you find this)
      • Note the opcode is 10, not 11 bits.
      • H&P say: Design Principle 3: Good design demands good compromises.
      • The additional bit, stolen from the opcode, as well as from the secondary op code give us 12 bits for the immediate
      • Or -2048 to 2047 (how did I get that?)
    • What is the opcode for addi?
      • 488₁₆-489₁₆
      • 488₁₆ = 100 1000 1000₂ 489₁₆ = 100 1000 1001₂
      • So we just ignore the last bit.
      • The opcode will be 100 1000 100
    • The immediate is 000000000001₂
    • Rn and Rd are both 01001₂
    • So the instruction is

      •  1001000100 000000000001 01001 01001
         10010001000000000000010100101001
         1001 0001 0000 0000 0000 0101 0010 1001
          9     1   0    0    0    5    2     9
         

      • By the way, Gemini messed this up, humans 1, ai 0
      • H&P point out that the immediate is not signed,
        • This means we need both ADDI and SUBI
        • And we get all 12 bits for the immediate.
  • add x15, x8, x3
    • Instruction type?
      • What are the fields?
      • shamt Is the amout to shift the immediate by
      • This defaults to 0.
    • Bits for op-code?
    • Op-code
    • Registers?

    • 458 3 0 8 15
      100 0101 1000 00011 000000 01000 01111
      10001011000000110000000100001111
      1000 1011 0000 0011 0000 0001 0000 1111
                 

    • Gemini got this one right, when I congratulated it, the response was "Thank you! I appreciate you double-checking the binary breakdown with me. Teamwork makes the dream work when it comes to bit-level encoding!"
• In the next section they discuss logical operations
  • LSL, LSR, AND, ANDI, OR, ORI, EOR, EORI
  • These are R-Type and I-Type
  • The shifts use the shamt fields.
  • They note where they have departed from ARM
    • ARM uses Add (shifted) as we discussed before
    • But for pedagogical purposes, this makes the data path too hard.
    • So they added these to LEG