A latch is a sequential circuit that changes its value immediately
a flip flop is a sequential circuit that changes its value when a "clock" goes from low to high.
In general we will use flip flops, but we will start with latches.
The most basic latch is the s-r latch
There are several ways to build this.
One is formed by hooking two nand gates together.
But inverting the switched inputs.
But the output of each serves as one input to the other.
In general, we do not allow both S and R to be high
Note that this is a latch as there is no "clock" signal.
An additional step is to add an enable signal
Which we will morph into a clock later.
A D latch
Set and reset are nice.
But normally we just want to store the data on a wire.
The D-Latch accomplishes this.
This is sort of pointless unless we have an enable line as well.
Note that this is still a latch
In general, we only want the values of these types of circuits to change at a given point.
Think about the start of the CPU circuit from last time
We are in the last stages of acc ← acc - B
We are moving the data from the ALU to the ACC
But we don't want to latch this
If we did, we would have a loop (think about it)
The acc would update, then a new value would go to the alu, which would put a new value on the bus which would update the acc, then the new value would go to the alu ...
If we only allow the acc to update once, ON THE CLOCK pulse, this would not be a problem.
Thus we want flipflops, not latches.
The R-S flipflop
Set the value of r or s
Then change the clock from low to high.
Note, Q will not change otherwise.
Implementing the R-S flipflop
When the clock is low, the first rs-latch records whaever the input stores.
When the clock changes from low to high, the first latch will no longer accept input, but the second latch will now do so.
This is called leader-follower design, but in the past was called master-slave.
We can implement a D flipflop in a similar way.
There are several other types of flipflops
The JK flipflop fixes a problem with sr
The input of 1,1 for a sr flipflop is non-deterministic
Actually that is not true, it depends on how the flip flop/latch is implementd.
JK fixes this, if the input is 1,1 the state does not change.
