CPU Review.

• A theoretical CPU is built from the following components:
  • Register file, or registers.
    • Temporary storage for a program.
    • In MIPS there are 32 of these.
    • Called General Purpose Registers.
  • ALU: Arithmetic Logic Unit
    • Performs the mathematics.
  • MMU: Memory Management Unit
    • Interacts with memory
  • IR: Instruction Register
    • Stores the current instruction.
  • PC: Program Counter
    • Stores the address of the next instruction to be executed
  • CU: Control Unit
    • Controls the operation of the other parts of the CPU
  • Bus
    • Data communications channel.
• Fetch-Decode-Execute cycle
  • RTN: Register Transfer Notation
  • Fetch:
    • BUS <- PC
      • PC <- PC +1
      • MAR <- BUS
    • LOAD
    • MDR <- memory[MAR]
    • BUS <- MDR
    • IR <- BUS
  • Decode: The CU examines the instruction in the IR and "decides" what to do.
  • Execute: Execute the instruction.
    • Example: LW $R1, 100($R4)
      • BUS <-R4
      • ALU₁ < BUS
      • BUS <- IR_15-0
      • ALU₂ <- BUS
      • PAD ALU₂ With 16 zeros.
      • Add
      • BUS <- ALU_OUT
      • MAR <- BUS
      • LOAD (MDR <- M[MAR])
      • BUS <- MDR
      • R1 <- BUS
• There are a number of different architectures on the market today
  • Intel/AMD support the same external architecture
  • Mips mostly in datacomm equipment today.
  • ARM probably in your phone.
  • Amazon graviton.
  • I am sure that there are more, but I am having trouble finding a good reference.
  • There were many others in the past.
  • Appendix E presents a survey of past processors.
• A few terms
  • CISC - Complex instruction set computer
    • see the x86 instruction set reference for integer add.
  • RISC - Reduced instruction set computer
    • add rd, rs1, rs2
    • add rd, rs1, imm16
  • Load/Store architecture
    • An architecture where the only instructions that access memory are load/store
    • Most likely a RISK architecture
• Stepping out from the processor we have
  • Memory
  • Hard Drives/Permanent storage
  • Other devices
  • Cache : a temporary collection of data attempting to speed up interactions between levels.
    • Memory to cpu is the most common
    • L1, L2, L3, ....