Pipeline Hazards

• A pipeline hazard is a condition that causes a delay in the execution of instructions in the pipeline.
• We will discuss three of these.
  1. Structural hazards, when a planned instruction can not execute in the proper clock cycle because the hardware does not support the combination of instructions that are set to execute: MIPS has none of these.
  2. Data hazards, when the planned instruction can not execute in the proper clock cycle because the data that is needed to execute the instruction is not yet available. MIPS has several of these.
  3. Control hazards, when the instruction can not execute in the proper clock cycle because the instruction that was fetched is not the instruction that was needed. MIPS has these as well.
• Structural Hazards
  • What if IF were a variable cycle operation?
  • What if there were only one memory access?
  • What if there were only one adder available?
  • What if fetch from the RF took the full clock cycle?
  • Fortunately none of these are part of the MIPS architecture.
  • There are no structural hazards in the MIPS architecture.
• Data Hazards
  • Let's trace the following instructions:

  •  
    I1: add $t1, $t2, $t3
    I2: add $s2, $t2, $t3
    I3: sw  $t1, 0($s2) 

  • Time	IF	ID	ALU	MEM	WB
    1	add $t1, $t2, $t3
    2	add $s2, $t2, $t3	add $t1, $t2, $t3
    3	sw $t1, 0($s2)	add $s2, $t2, $t3	add $t1, $t2, $t3
    4		sw $t1, 0($s2)	add $s2, $t2, $t3	add $t1, $t2, $t3
    5			sw $t1, 0($s2)	add $s2, $t2, $t3	add $t1, $t2, $t3
    6				sw $t1, 0($s2)	add $s2, $t2, $t3
    7					sw $t1, 0($s2)

  • The third instruction has two data dependencies.
    • It needs the result of the second add for the address at ID (time 4) , but this won't be in the register until I₂ hits WB, (time 6).
    • It needs the result of the first add for the word to store at ID (time 4), but this won't be available until I₁ hits WB, (time 5).
  • The naive solution is to stall the pipeline.

  • Time	IF	ID	ALU	MEM	WB
    1	add $t1, $t2, $t3
    2	add $s2, $t2, $t3	add $t1, $t2, $t3
    3	sw $t1, 0($s2)	add $s2, $t2, $t3	add $t1, $t2, $t3
    4		sw $t1, 0($s2)	add $s2, $t2, $t3	add $t1, $t2, $t3
    5		sw $t1, 0($s2)		add $s2, $t2, $t3	add $t1, $t2, $t3
    6		sw $t1, 0($s2)			add $s2, $t2, $t3
    7			sw $t1, 0($s2)
    7				sw $t1, 0($s2)
    7					sw $t1, 0($s2)

  • A stall is not hard to implement.
    • We insert a bubble or noop into the pipeline.
    • We just insert 0 into the control signals for the instruction we are turning into a bubble.
    • And we don't move the stalled instruction data ahead in the pipeline
    • See the image on page 323.
  • But this is probably bad!, it defiantly increases the CPI
  • Do other examples exist?
    • Where is data produced in the pipeline?
    • Where id data consumed in the pipeline?
    • Use the picture on page 301
    • Can you construct a set of instructions that causes each problem.
  • The solution is data forwarding.
    • First we need to identify where the data hazard occurs.
    • Then we need to forward the data to the proper place.
    • How would we deal with this?
  • Can we handle all data problems?
    • lw is a problem.

    • I1: lw $rx, xxx
      I2: add $XX, $rx, $rx
                 

    • Time	IF	ID	ALU	MEM	WB
      1	I1
      2	I1	I1
      3		I2	I1
      4		I2		I1

    • At the end of T₄ we have the data, so we could forward it
    • But there is no way to have it sooner.
  • Thus after a load, we should not have an instruction that uses that data.
    • The instruction immediately following a load is in the load delay slot.
    • If it uses the result of the load, it must be stalled, causing these instructions to have a CPI of 2.
  • What can we do about this?
    • The hardware can only detect this, and insert a bubble if needed.
    • BUT the compiler could adjust the instructions to fill this slot with another instruction.
  • Consider the following program

    .data
    
    MYDATA:	.word 100 200 300 400
    MAX_SIZE: .word 4
    
    .text
    
    .globl main
    
    main:
    
    	la 	$a0, MYDATA # base address of the array
    	li	$t0, 0   # offset into the array
    	li	$t1, 0   # index into the array
    	
    	lw	$t2, MAX_SIZE  # loop limit
    
     top:
     	beq	$t1, $t2, done 
     	
     		add	$t3, $a0, $t0
     		lw	$a1, 0($t3)
     		addi	$a1, $a1, 101
     		sw	$a1, 0($t3)
     		
     		addi	$t0, $t0, 4
     		addi	$t1, $t1, 1
     		b 	top
     done:
     	li $v0, 10
     	syscall 

  • Identify the load delay slot(s)
  • Identify instructions we can move to fill these slots.
  • You can solve this problem by rearranging instructions MOST of the time.
  • Occasionally you will need to insert a noop in the load delay slot.
• The compiler needs to know about the architecture to be able to generate
• I believe that mars ignores the load delay slot.