Pipeline Overview

• This is 4.6 -> read it.
• We can divide the MIPS processor we have been looking at into 5 pieces.
  • IF - instruction fetch.
    • Fetch the instruction from memory
    • Increment the pc
  • ID - instruction decode, but second half of cycle
    • Decode the opcode issue control signals
    • Get values from the register file.
  • ALU (the book calls this EX, but I probably will not)
    • Do whatever math is needed for the operation.
  • Mem
    • Perform any memory operations on data.
  • WB - write back.
    • Store any data produced back into the register file.
• A good picture of this is on page 301
  • We use register type memory to store the "state" of the machine between stages of the pipeline.
  • At the beginning of the instruction, we read from the proceeding memory
  • At the end, we write the data produced in the following memory.
• On 288 they present some idealized data on each functional unit.
  • IF, ALU, MEM are all 200 ps operations
  • ID and WB are 100 PS operations.
  • So an ideal single instruction machine would require 800ps per instructions.
  • With a CPI of 1.
• If we pipeline

  • Time	IF	ID	ALU	MEM	WB
    1	I1
    2	I2	I1
    3	I3	I2	I1
    4	I4	I3	I2	I1
    5	I5	I4	I3	I2	I1
    6	I6	I5	I4	I3	I2
    7	I7	I6	I5	I4	I3

  • Instruction 1 finishes in 5 step (4+1) .
  • Instruction 2 finishes in 6 steps (4+2).
  • Instruction 3 finishes in 7 steps, or (4+3)
  • Instruction n finishes in 4+n steps.
  • But the cycle time can be reduced to 200ps.
  • And, for this second, cpi = 1
• So

  For an $n$ instruction program:
  
  $T_s = 800n$
  $T_p = 200(n+4)$
  
  $\text{Speedup} =  \frac{800n}{200n +800} \approx 4$ 

• This works because of three properties of the mips instruction set
  • All instructions are the same size
    • We fetch the next instruction without any "intelligence"
    • If instructions were different sizes
      • Fetch the op-code to determine instruction size
      • Fetch the rest of the instruction.
    • This would cause delays at best and make it very complex at least.
  • The layout of the instructions is similar
    • So we can get data from the RF even before we know what the op-code is.
  • There is at most one memory operation per instruction.
    • variable number of memory operations would again make the instruction hard to implement in the pipeline.
• The big idea is that all instructions can be executed in roughly the same amount of time.