Because of the possibility of transmission errors, and because the receiver of data may need to regulate the rate at which data arrives, synchronization and interfacing techniques are insufficient by themselves. It is necessary to impose a layer of control in each communicating device that provides functions such as flow control, error detection and error control. This layer of
control is known as data link control protocol.
Flow control enables a receiver to regulate the flow of data from a
sender so that the receiver's buffers do not overflow.
Error detection is performed by calculating an error-detection code
that is a function of the bits being transmitted. The code is appended to the transmitted bits. The receiver calculates the code based on the incoming bits and compares it to the incoming code to check for errors.
In a data link control protocol, error control is achieved by retransmission of damaged frames that have not been acknowledged or for which the other side requests a retransmission.
Some things that interfacing can not deal with. Or Why we need this
chapter.
Frame synchronization - need to recognize the beginning of a frame
Flow Control
Error Control
Addressing
Control and Data information separation (Know what is data and what is a control message)
Link Management - set up a session, coordination a session, destroy a session
Flow Control
Buffers are involved with the transmission of data
Sender's buffer
Receiver's buffer
We don't want to overflow either
The sender has control of filing it's own buffer and
can slow down when it fills.
The receiver can has no direct control over how fast the
sender sends, and if it does not consume the data fast
enough, there will be problems
Queuing Theory
In this image
Frames are sent from the source to the destination
Frame F2 is lost in transmission
Frame F4 is garbled
This is how the system changes over time
The time it takes a station to put all of the bits of the
frame on the transmission media is transmission time
This is proportional to the length of the frame
The time it takes for a bit to traverse the network is propagation time
This system is not deterministic, there are nondeterminstic
delays due to queues
Stop and wait flow control.
Simple Idea
Source: Send a frame
Destination: Receive the frame
Destination: Acknowledge the frame
Source: Receive the Acknowledgment, go to step 1.
This is good for a few large frames
Large frames are a problem
Network Congestion
Better chance of error in each frame
Buffer Requirements
Total time for a frame is:
a = propagation time
t0 = transmission time.
To send a frame
t0 to put the frame on the network
a for the last bit to propagate through the network
The time for the acknowledgment to return (a)
T = t0+2a
Notice that this gets worse as a increases
Long distances between stations
Slow data rates
And is bad anytime that a>t0, because the
network is not fully occupied.
So in a fast network, we spend most of the time waiting for
an acknowledgment.
This probably renders this system unacceptable.
Sliding Window Flow Control
Allow multiple frames to be in transit at a time
This is an attempt to fix the problem fin stop in wait.
Each participant must have buffer space for multiple frames
Assume this is W frames
The source can send W frames without an acknowledgment
The destination returns an acknowledgment for multiple frames
at a time
Only W frames can be outstanding (unacknowledged) at any time.
The acknowledgment contains a number n telling the source
that frames up to frame n have been received.
The source must maintain a list of frames that have been
sent but not acknowledged (and the frames as well)
The destination maintains a list of frames it is prepared
to receive.
These two lists are thought of as a "window"
So this system is called sliding window flow control.
Serial numbers require some attention
The more bits we use to encode a serial number, the fewer
we have for data
Depending on the window size, we can use 3, 4, or 5 bits.
All math is done mod 2k-1
Two types of acknowledgments
RR n - I have received all frames up to (but not including n) and can continue to receive frames
RNR n - I have received all frames up to (but not including) n, but am not ready to receive any more frames.
A RR is required to restart after a RNR
Example
Assume a window of 2 bits (7 frames in window)
Source transmits frames F0 - F4
F0-F4 are still buffered on the server
It still can transmit F5-F6
Destination Receives Frames F0-F3 (4 is in transit)
Destination sends RR 4 (I have received 0-3)
Source sends F5 (it can still send F6)
Source receives RR 4, It can now dispose of Frames 0-3
And generate and send frames F7-F2
Error Detection
Start with some definitions
Pb is the probability of a single bit error (BER)
P1 is the probability of a frame arriving with no error
P2 is the probability of a frame arriving with one error, that are undetected.
P3 is the probability of a frame arriving with one error, that are detected.
F is the number of bits per frame.
With no error detection
P1 = (1-Pb)F
P2 = 1-P1
As Pb goes up, P1 goes down
As F goes up, P1 goes down.
For example
Atm operates at 155Mbps, 53 byte frame
Assume Pb = 1x10-8
F = 53*8 = 424
P1 = .999996
P2 = 4.24x10-6
FPS = .36x106
Estimated Errors per second = 1.5 = 2
This is 93 errors per min or 5580 errors per hour.
It seems clear to me that we need some form of error detection.
To do this the transmitter adds error detection bits to every frame
These bits are calculated based on the contents of a frame
The receiver performs the same calculation when it receives the
frame and compares the value it calculated with the bits in the frame
Example Parity Bit
This can go wrong, and we can mess things up.
Two consecutive bits are flipped with parity check.
P3 becomes something we are interested in
CRC
Cyclic Redundancy Check
Given a k bit frame
Generate n, a bit sequence such that
(frame+nbits)% P = 0
Where P is a predetermined value.
Assume P = 9
The added bits are called the frame control sequence (FCS)
Just to make things flaky, adds and subtracts are
done without a carry.
1011 1011
+1101 +1011
---- -----
0110 0000
An interesting fact is 2N/P mod 2 = 0
This is a xor
Multiplying by 2 is a shift left
Divide by 2 is a shift right
T the total message
M is the payload
F the FCS
T = 2nM+F
P as above
2nM/P = Q + R/P
Let F = R/P
T = 2n+R/P
T/P = (2n+R)/P = 2nM/P +R/P
T/P = Q + R/P + R/P = Q + 2R/P
= Q (by the add example above)
So R is an acceptable FCS
P n+1 bits long, and must start and end with a 1
Polynomials
Again M is our message M=bk-1bk-2 ... b1b0
M(X) =
bk-1Xk-1 +
bk-2Xk-2 + ... +
b1X1 +
b0X0
If M = 11010, M(X) = X4+X3+X
Do math modulo 2
The CRC is calculated
XnM(X) / P(X) = Q(X) + R(X)/P(X)
T(X) = XnM(X) + R(X)
E(X) is the transmitted message, with error
E(X) is undetectable if it is divisible by P(X)
A good P(X) will detect
All single bit errors
All double bit errors
Any odd number of errors
Some good P(X)
CRC-12 = X12+X11+X3+X2+X+1
CRC-16 = X16+X15+X2+1
CRC-CCITT = X16+X12+X5+1
CRC-32 as well
CRC-12 generates a 12 bit FCS
CRC-16 and CCITT generate 16 bit FCS
CRC-32 generates a 32 bit FCS
Digital Logic
For each bit in the pattern, excluding the MSB, we xor
the output from the previous flip-flop with the MSB to
find the new value for the next flip flop.
This circuit implements the division mod 2 algorithm.
(For the pattern 1001)
it can both check (all bits are 0)
Or generate, The three bits stored in the register are R
Error Control
Detect and correct errors that occur in the transmission of a frame
We consider:
Lost Frame - frame that does not arrive
Damaged Frame - frame that is not correctable
And we will perform the following
Error Detection, as above
Positive Acknowledgment as before - Destination
Retransmit on Timeout - Source
Negative Acknowledgment and Retransmission - Destination, Source
This turns an unreliable data link into a reliable datalink
This is called Automatic Repeat Request (ARQ)
Three ARQ standards
Stop and wait ARQ
As you think.
Source has a timer, if it does not receive an ACK in a given
amount of time, it resends the frame
Duplicate frames on the destination side are discarded.
(but acknowledged)
Frames with errors are not acknowledged
Windows are applicable here too.
go back n ARQ
A sliding window
Regular fames are acknowledged
A REJ - reject is sent for frames with errors
All frames are discarded until the rejected frame is retransmitted
Selective Reject ARQ
Only bad frames are rejected
Destination is responsible for correct order to upper layers
Requires a much larger buffer
High Level Data Link Control (HDLC)
This is an example of a Data Link protocol
It is the basis for many other protocols
Basic Characteristics
Three types of stations
Primary - controls the link - Send
Secondary - reply
Combined - both
Two Link Types
Unbalanced - 1 primary, 1 or more secondary
Balanced - two combined stations
Three data transfer modes
Normal response mode
Used for unbalanced configuration
Primary must initiate transfer
Secondary only responds to primary
Terminals connected to a machine
Machine polls machines for input
Asynchronous balanced mode
Balanced configuration
Either may initiate transmission
Point to point link
Asynchronous response mode
Unbalanced configuration
Secondary initiates transmission
Primary is still in charge of line
Frame Structure
Flag Fields (first and last 8 bits)
Pattern 011111110.
Closing of one frame can be the opening of another.
When sending a string of 6 bits, change the last to a 0
This bit is deleted on receipt
5 ones followed by 10 means end of frame
5 ones followed by 11 means abort condition
...01111111..
is sent as ...011111011...
and becomes ...01111111...